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| 1 ? march 1997 80c286 high performance microprocessor with memory management and protection features ? compatible with nmos 80286 wide range of clock rates - dc to 25mhz (80c286-25) - dc to 20mhz (80c286-20) - dc to 16mhz (80c286-16) - dc to 12.5mhz (80c286-12) - dc to 10mhz (80c286-10) static cmos design for low power operation - iccsb = 5ma maximum - iccop = 185ma maximum (80c286-10) 220ma maximum (80c286-12) 260ma maximum (80c286-16) 310ma maximum (80c286-20) 410ma maximum (80c286-25) high performance processor (up to 19 times the 8086 throughput) large address space 16 megabytes physical/1 gigabyte virtual per task integrated memory management, four-level memory protection and support for virtual memory and operat- ing systems two 80c86 upward compatible operating modes - 80c286 real address mode -pvam compatible with 80287 nu meric data co-processor high bandwidth bus interface (25 megabyte/sec) available in - 68 pin pga (commercial, industrial, and military) - 68 pin plcc (commercial and industrial) description the intersil 80c286 is a stat ic cmos version of the nmos 80286 microprocessor. the 80c286 is an advanced, high- performance microprocessor with specially optimized capa- bilities for multiple user a nd multi-tasking systems. the 80c286 has built-in memory prot ection that supports operat- ing system and task isolation as well as program and data privacy within tasks. a 25mhz 80c286 provides up to nine- teen times the throughput of a standard 5mhz 8086. the 80c286 includes memory management capabilities that map 2 30 (one gigabyte) of virtual address space per task into 2 24 bytes (16 megabytes) of physical memory. the 80c286 is upwardly compatible with 80c86 and 80c88 software (the 80c286 instruction set is a superset of the 80c86/80c88 instruction set). using the 80c286 real address mode, the 80c286 is object code compatible with existing 80c86 and 80c88 software. in protected virtual address mode, the 80c286 is source code compatible with 80c86 and 80c88 software but may require upgrading to use virtual address as supported by the 80c286?s integrated memory management and protection mechanism. both modes operate at full 80c286 performance and execute a superset of the 80c86 and 80c88 instructions. the 80c286 provides special operations to support the effi- cient implementation and exec ution of operating systems. for example, one instruction can end execution of one task, save its state, switch to a new task, load its st ate, and start execution of the new task. the 80c286 also supports virtual memory systems by providing a segment-not-present excep- tion and restartable instructions. ordering information package temp. range 10mhz 12.5mhz 16mhz 20mhz 25mhz pkg. no. pga 0 o c to +70 o c - cg80c286-12 cg80c286-16 cg80c286-20 - g68.b -40 o c to +85 o c ig80c286-10 ig80c286-12 - - - g68.b -55 o c to +125 o c 5962- 9067801mxc 5962- 9067802mxc ---g68.b plcc 0 o c to +70 o c - cs80c286-12 cs80c286-16 cs80c286-20 cs80c286-25 n68.95 -40 o c to +85 o c is80c286-10 is80c286-12 is80c286-16 is80c286-20 - n68.95 fn2947.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a registered trademark of intersil americas inc. copyright ? intersil americas inc. 2003. all rights reserved all other trademarks mentioned are the property of their respective owners.
2 pinouts 68 lead pga component pad view - as viewed from underside of the component when mounted on the board. 68 lead pga p.c. board view - as viewed from the component side of the p.c. board. 68 66 64 62 60 58 56 54 52 53 51 55 57 59 61 63 65 67 2 1 3 5 7 9 10 4 6 8 12 11 13 14 16 15 17 19 18 21 20 22 24 26 28 30 32 34 23 25 27 29 31 33 36 35 37 38 40 39 41 42 44 43 45 46 48 47 49 50 error d7 d6 d5 d4 d3 d2 d1 d0 nc s1 peack a22 a21 a19 a17 a15 a12 d0 a1 clk reset a4 a6 a8 a10 a12 error nc intr nmi pereq ready hlda m/io nc nc busy nc nc v ss v cc hold cod/inta lock d15 d14 d13 d12 d11 d10 d9 d8 v ss bhe nc s0 a23 v ss a20 a18 a16 a14 a0 a2 v cc a3 a5 a7 a9 a11 a13 pin 1 indicator 68 66 64 62 60 58 56 54 52 53 51 55 57 59 61 63 65 67 2 13 579 10 4 68 12 11 13 14 16 15 17 19 18 21 20 22 24 26 28 30 32 34 23 25 27 29 31 33 36 35 37 38 40 39 41 42 44 43 45 46 48 47 49 50 error d7 d6 d5 d4 d3 d2 d1 d0 nc s1 peack a22 a21 a19 a17 a15 a12 d0 a1 clk reset a4 a6 a8 a10 a12 error nc intr nmi pereq ready hlda m/io nc nc busy nc nc v ss v cc hold cod/inta lock d15 d14 d13 d12 d11 d10 d9 d8 v ss bhe nc s0 a23 v ss a20 a18 a16 a14 a0 a2 v cc a3 a5 a7 a9 a11 a13 pin 1 indicator 80c286 3 68 lead plcc p.c. board view - as viewed from the component side of the p.c. board. functional diagram pinouts (continued) 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 d15 d7 d14 d6 d13 d5 d12 d4 d11 d3 d10 d2 d9 d1 d8 d0 v ss bhe nc nc s1 s0 peack a23 a22 v ss a21 a20 a19 a18 a17 a16 a15 a14 lock m/io cod/inta hlda hold ready v cc pereq v ss nmi nc intr nc nc busy error nc a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 reset v cc clk a2 a1 a0 offset adder segment limit checker segment bases segment sizes physical address adder alu control registers address latches and drivers pre- bus control fetcher processor extension interface data transceivers 6-byte prefetch queue instruction unit (iu) bus unit (bu) execution unit (eu) address unit (au) a 23 - a 0 , bhe , m/io peack 3 decoded instruction queue instruction decoder pereq ready , hold, s1 , s0 , cod/inta, lock, hlda d 15 - d 0 reset clk v ss v cc nmi busy error intr 80c286 4 pin descriptions the following pin function descriptions are for the 80c286 microprocessor. symbol pin number type description clk 31 i system clock: provides the fundamental timing for the 80c286 system. it is divided by two inside the 80c286 to generate the processor clock. the in ternal divide-by-two ci rcuitry can be synchro- nized to an external clock generator by a low to high transition on the reset input. d 15 - d 0 36 - 51 i/o data bus: inputs data during memory, i/o , and interrupt acknowledge read cycles; outputs data during memory and i/o write cycles. the data bus is active high and is held at high impedance to the last valid logic level during bus hold acknowledge. a 23 - a 0 7 - 8 10 - 28 32 - 43 o address bus: outputs physical memory and i/o port addresses. a 23 - a 16 are low during i/o transfers. a 0 is low when data is to be transferred on pins d 7 - d 0 (see table below). the address bus is active high and floats to thr ee-state off during bus hold acknowledge. bhe 1 o bus high enable: indicates transfer of data on the upper byte of the data bus, d 15 - d 8 . eight-bit oriented devices assigned to the upper byte of the data bus would normally use bhe to condition chip select functions. bhe is active low and floats to three-state off during bus hold acknowledge. s1 , s0 4, 5 o bus cycle status: indicates initiation of a bus cycle and along with m/io and cod/lnta , de- fines the type of bus cycle. the bus is in a t s state whenever one or both are low. s1 and s0 are active low and are held at a high impe dance logic one during bus hold acknowledge. bhe and a 0 encodings bhe value a 0 value function 0 0 word transfer 0 1 byte transfer on upper half of data bus (d 15 - d 8 ) 1 0 byte transfer on lower half of data bus (d 7 - d 0 ) 11reserved 80c286 bus cycle status definition cod/inta m/io s1 s0 bus cycle initiated 0(low) 0 0 0 interrupt acknowledge 0001reserved 0010reserved 0 0 1 1 none; not a status cycle 0 1 0 0 if a 1 = 1 then halt; else shutdown 0 1 0 1 memory data read 0 1 1 0 memory data write 0 1 1 1 none; not a status cycle 1(high) 0 0 0 reserved 1 0 0 1 i/o read 1 0 1 0 i/o write 1 0 1 1 none; not a status cycle 1100reserved 1 1 0 1 memory instruction read 1110reserved 1 1 1 1 none; not a status cycle 80c286 5 m/io 67 o memory i/o select: distinguishes memory access from i/o access. if high during t s , a mem- ory cycle or a halt/shutdow n cycle is in progress. if low, an i/o cycle or an interrupt acknowledge cycle is in progress. m/io is held at high impedance to the last valid logic state during bus hold ac- knowledge. cod/lnta 66 o code/interrupt acknowledge: distinguishes instruction fetc h cycles from memory data read cycles. also distinguishes interrupt acknowledge cycles from i/o cycles. cod/lnta is held at high impedance to the last valid logic state during bus hold acknowledge. its timing is the same as m/io . lock 68 o bus lock: indicates that other system bus mast ers are not to gain control of the system bus for the current and following bus cycles. the lock signal may be activated explicitly by the ?lock? instruction prefix or automatically by 80c286 hard ware during memory xchg instructions, interrupt acknowledge, or descriptor table access. lock is active low and is held at a high impedance logic one during bus hold acknowledge. ready 63 l bus ready: terminates a bus cycle. bus cycles are extended wi thout limit until terminated by ready low. ready is an active low synchr onous input requiring setup and hold times relative to the system clock be met fo r correct operation. ready is ignored during bus hold acknowledge. (see note 1) hold hlda 64 65 i o bus hold request and hold acknowledge: control ownership of the 80c286 local bus. the hold input allows another loca l bus master to request control of the local bus. when control is granted, the 80c286 will float its bus drivers and t hen activate hlda, thus entering the bus hold ac- knowledge condition. the local bus will remain granted to the requesting master until hold be- comes inactive which results in the 80c286 deac tivating hlda and regaining control of the local bus. this terminates the bus hol d acknowledge condition. hold may be asynchronous to the sys- tem clock. these signals are active high. note that hlda never floats. intr 57 i interrupt request: requires the 80c286 to su spend its current program execution and service a pending external request. interrupt requests are masked whenever the interrupt enable bit in the flag word is cleared. when the 80c286 responds to an interrupt request, it performs two interrupt acknowledge bus cycles to read an 8-bit interrupt ve ctor that identifies the source of the interrupt. to ensure program interruption, intr must rema in active until an interrupt acknowledge bus cycle is initiated. intr is sampled at the beginning of each processor cycle and must be active high at least two processor cycles before the current instru ction ends in order to interrupt before the next instruction. intr is level sensitive, active hi gh, and may be asynchronous to the system clock. nmi 59 l non-maskable interrupt request: interrupts t he 80c286 with an inter nally supplied vector value of two. no interrupt acknowledge cycles are performed. the interrupt enable bit in the 80c286 flag word does not affect this input. the nmi inpu t is active high, may be asynchronous to the sys- tem clock, and is edge triggered afte r internal synchronization. for proper recognition, the input must have been previously low for at least four system clock cycles and remain high for at least four system clock cycles. pereq peack 61 6 l o processor extension operan d request and acknowledge: extend the memory management and protection capabilities of the 80c 286 to processor extensions. the pereq input requests the 80c286 to perform a data operand tr ansfer for a processor extension. the peack out- put signals the processor extension when the reques ted operand is being transferred. pereq is ac- tive high. peack is active low and is held at a high impedance logic one during bus hold acknowledge. pereq may be asynchronous to the system clock. busy error 54 53 l i processor extension busy and error: indica tes the operating condition of a processor extension to the 80c286. an active busy input stops 80c286 program execution on wait and some esc instructions until busy becomes inactive (high). the 80c286 may be interrupted while waiting for busy to become inactive. an active error input causes the 80c286 to perform a pro- cessor extension interrupt when ex ecuting wait or some esc instru ctions. these inputs are active low and may be asynchronous to the system clock. pin descriptions the following pin function descriptions are for the 80c286 microprocessor. (continued) symbol pin number type description 80c286 6 functional description introduction the intersil 80c286 microprocessor is a static cmos ver- sion of the nmos 80286 microprocessor. the 80c286 is an advanced, high-performance mi croprocessor with specially optimized capabilities for multip le user and multi-tasking sys- tems. depending on the application, the 80c286's perfor- mance is up to nineteen times faster than the standard 5mhz 8086's, while providing complete upward software compatibility with intersil 80c86 and 80c88 cpu family. the 80c286 operates in two modes: 80c286 real address mode and protected virtual address mode. both modes exe- cute a superset of the 80c86 and 80c88 instruction set. in 80c286 real address mode programs use real addresses with up to one megabyte of address space. programs use vir- tual addresses in protected virtual address mode, also called protected mode. in protected mode, the 80c286 cpu automat- ically maps 1 gigabyte of virtual addresses per task into a 16 megabyte real address space. this mode also provides mem- ory protection to isolate the operating system and ensure pri- vacy of each tasks' programs and data. both modes provide the same base instruction set, registers and addressing modes. the functional description describes the following: static oper- ation, the base 80c286 architecture common to both modes, 80c286 real address mode, and finally, protected mode. static operation the 80c286 is comprised of completely static circuitry. internal registers, counters, and latches are static and require no refresh as with dynam ic circuit design. this elim- inates the minimum operating frequency restriction typically placed on microprocessors. the cmos 80c286 can oper- ate from dc to the specified upper frequency limit. the clock to the processor may be stopped at any point (either phase one or phase two of the processor clock cycle) and held there indefinitely. there is, however, a significant decrease in power requirement if the clock is stopped in phase two of the processor clock cycle. details on the clock relationships will be discussed in the bus operation sec- tion. the ability to stop the clock to the processor is espe- cially useful for system debug or power critical applications. reset 29 l system reset: clears the internal logic of the 80c286 and is active high. the 80c286 may be reinitialize at any time with a low to high trans ition on reset which remains active for more than 16 system clock cycles. during reset active, the output pins of the 80c286 enter the state shown below. operation of the 80c286 begins after a hlgh to low transition on reset. the high to low transition of reset must be synchronous to the system clock. approximately 50 system clock cycles are required by the 80c286 for internal initia lizations before the first bus cycle to fetch code from the power-on execution address is performed. a low to high transition of reset synchronous to the syste m clock will end a processor cycle at the second high to low transition of the system clock. the low to high transit ion of reset may be asynchronous to the system clock; however, in this case it cannot be predetermi ned which phase of the processor clock will occur during the next system clock peri od. synchronous low to high tran sitions of reset are required only for systems where the processor clock must be phase synchronous to another clock. v ss 9, 35, 60 l system ground: are the ground pins (all must be connected to system ground). v cc 30, 62 l system power: +5v power supply pins. a 0.1 f capacitor between pins 60 and 62 is recommended. notes: 1. ready is an open-collector signal and should be pu lled inactive with an appropriate resistor (620 ? at 10mhz and 12.5mhz, 470 ? at 16mhz, 390 ? at 20mhz, 270 ? at 25mhz). 2. hlda is only low if hold is inactive (low). 3. all unused inputs should be pulled to their i nactive state with pull up/down resistors. pin descriptions the following pin function descriptions are for the 80c286 microprocessor. (continued) symbol pin number type description 80c286 pin state during reset pin value pin names 1 (high) s0 , s1 , peack , a 23 - a 0 , bhe , lock 0 (low) m/io , cod/lnta , hlda (note 2) high impedance d15 - d0 80c286 7 the 80c286 can be single-stepped using only the cpu clock. this state can be maintained as long as necessary. single step clock information allows simple interface circuitry to provide critic al information for system debug. static design also allows very low frequency operation (down to dc). in a power critical situation, this can provide low power operation since 80c286 power dissipation is directly related to operating frequency. as the system frequency is reduced, so is the operating power until, ultimately, with the clock stopped in phase two of the processor clock cycle, the 80c286 power requirement is the standby current (5ma maximum). 80c286 base architecture the 80c86, 80c88, and 80c286 cpu family all contain the same basic set of registers, instructions, and addressing modes. the 80c286 processor is upwardly compatible with the 80c86 and 80c88 cpu's. register set the 80c286 base architecture has fifteen registers as shown in figure 1. these registers are grouped into the fol- lowing four categories. general registers: eight 16-bit general purpose regis- ters used to contain arithmetic and logical operands. four of these (ax, bx, cx and dx) can be used either in their entirety as 16-bit words or split into pairs of separate 8-bit registers. segment registers: four 16-bit special purpose regis- ters select, at any given time , the segments of memory that are immediately addressable for code, stack and data. (for usage, refer to memory organization.) base and index registers: four of the general pur- pose registers may also be used to determine offset addresses of operands in memory. these registers may con- tain base addresses or indexes to particular locations within a segment. the addressing mode determines the specific registers used for operand address calculations. status and control registers: three 16-bit special purpose registers record or co ntrol certain aspects of the 80c286 processor state. these include the flags register and machine status word register shown in figure 2, and the instruction pointer, which contains the offset address of the next sequential instruction to be executed. flags word description the flags word (flags) records specific characteristics of the result of logical and arithmetic instructions (bits 0, 2, 4, 6, 7 and 11) and controls the oper ation of the 80c286 within a given operating mode (bits 8 and 9). flags is a 16-bit regis- ter. the function of the flag bits is given in table 1. ah al dl cl bl dh ch bh ax dx cx bx bp si di sp byte addressable (8-bit register names shown) multiply/divide i/o instructions loop/shift/repeat base registers count index registers stack pointer 15 0 0 7 0 7 special register functions 16-bit register name general registers cs ds ss es 0 15 code segment segment registers selector data segment selector stack segment selector extra segment selector f 0 15 flags instruction machine pointer status word ip msw status and control registers figure 1. register set 80c286 8 table 1. flags word bit functions bit position name function 0 cf carry flag - set on high-order bit carry or borrow; cleared otherwise. 2 pf parity flag - set if low-order 8 bits of result contain an even number of 1 bits; cleared otherwise. 4 af set on carry from or borrow to the low order four bits of al; cleared otherwise. 6 zf zero flag - set if result is zero; cleared otherwise. 7 sf sign flag - set equal to high-order bit of result (0 if positive, 1 if negative). 11 of overflow flag - set if result is a too-large positive number or a too-sm all negative number (excluding sign-bit) to fit in destination operand; cleared otherwise. 8 tf single step flag - once set, a single step interrupt occurs after the next instruction executes. tf is cleared by the single step interrupt. 9 if interrupt-enable flag - when set, maskable interrupts will cause the cpu to tr ansfer control to an inter- rupt vector specified location. 10 df direction flag - causes string instructions to auto decrement the appropriate index registers when set. clearing df causes auto increment. control flags: trap flag interrupt enable direction flag special fields: i/o privilege level nested task flag ts em mp pe cf pf af zf sf tf if df of iopl nt flags: 14 15 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 15 overflow sign zero auxiliary carry parity carry status flags: msw: reserved task switch processor extension emulated monitor processor extension protection enable figure 2. status and control register bit functions 80c286 9 instruction set the instruction set is divide d into seven categories: data transfer, arithmetic, string mani pulation, shift/rotate/logical, high level, processor control and control transfer instructions. these categories are summarized in table 2. an 80c286 instruction can reference zero, one, or two oper- ands; where an operand may reside in a register, in the instruction itself, or in memory. zero-operand instructions (e.g. nop and hlt) are usually one byte long. one-operand instructions (e.g. inc and dec) are usually two bytes long but some are encoded in only one byte. one-operand instructions may reference a register or memory location. two-operand instructions permit the following six types of instruction operations: register to register memory to memory memory to register register to memory immediate to register immediate to memory two-operand instructions (e.g. mov and add) are usually three to six bytes long. memory to memory operations are provided by a special class of string instructions requiring one to three bytes. for detailed instruction formats and encodings refer to the instruction set summary at the end of this document. table 2a. data transfer instructions general purpose mov move byte or word push push word onto stack pop pop word off stack pusha push all registers on stack popa pop all regist ers from stack xchg exchange byte or word xlat translate byte input/output in input byte or word out output byte or word address object lea load effective address lds load pointer using ds les load pointer using es flag transfer lahf load ah register from flags sahf store ah register in flags pushf push flags onto stack popf pop flags off stack table 2b. arithmetic instructions addition add add byte or word adc add byte or word with carry inc increment byte or word by 1 aaa ascli adjust for addition daa decimal adjust for addition subtraction sub subtract byte or word sbb subtract byte or word with borrow dec decrement byte or word by 1 neg negate byte or word cmp compare byte or word aas ascli adjust for subtraction das decimal adjust for subtraction multiplication mul multiply byte or word unsigned lmul integer multiply byte or word aam ascli adjust for multiply division dlv divide byte or word unsigned ldlv integer divide byte or word aad ascli adjust for division cbw convert byte to word cwd convert word to doubleword table 2c. string instructions movs move byte or word string ins input bytes or word string outs output bytes or word string cmps compare byte or word string scas scan byte or word string lods load byte or word string stos store byte or word string rep repeat repe/repz repeat while equal/zero repne/repnz repeat while not equal/not zero 80c286 10 table 2d. shift/rotate logical instructions logicals not ?not? byte or word and ?and? byte or word or ?inclusive or? byte or word xor ?exclusive or ? byte or word test ?test? byte or word shifts shl/sal shift logical/arithmetic left byte or word shr shift logical right byte or word sar shift arithmetic right byte or word rotates rol rotate left byte or word ror rotate right byte or word rcl rotate through carry left byte or word rcr rotate through carry right byte or word table 2e. high level instructions enter format stack for procedure entry leave restore stack for procedure exit bound detects values outside prescribed range table 2f. processor control instructions flag operations stc set carry flag clc clear carry flag cmc complement carry flag std set direction flag cld clear direction flag stl set interrupt enable flag cll clear interrupt enable flag external synchronization hlt halt until interrupt or reset wait wait for test pin active esc escape to extension processor lock lock bus during next instruction no operation nop no operation execution environment control lmsw load machine status word smsw store machine status word table 2g. program transfer instructions conditional transfers unconditional transfers ja/jnbe jump if above/not below nor equal call call procedure jae/jnb jump if above or equal/not below ret return from procedure jb/jnae jump if below/not above nor equal jmp jump jbe/jna jump if below or equal/not above jc jump if carry iteration controls je/jz jump if equal/zero loop loop jg/jnle jump if greater/not less nor equal jge/jnl jump if greater or equal/not less loope/loopz loop if equal/zero jl/jnge jump if less/not greater nor equal loopne/loopnz loop if not equal/not zero jle/jng jump if less or equal/not gr eater jcxz jump if register cx = 0 jnc jump if not carry jne/jnz jump if not equal/not zero interrupts jno jump if not overflow int interrupt jnp/jpo jump if not parity/parity odd jns jump if not sign into interrupt if overflow jo jump if overflow lret interrupt return jp/jpe jump if parity/parity even js jump if sign 80c286 11 memory organization memory is organized as sets of variable-length segments. each segment is a linear contiguous sequence of up to 64k (2 16 ) 8- bit bytes. memory is addressed using a two-component address (a pointer) that consists of a 16-bit segment selector and a 16-bit offset. the segment selector indicates the desired segment in memory. the offset component indicates the desired byte address within the segment. (see figure 3). all instructions that address op erands in memory must spec- ify the segment and the offset. for speed and compact instruction encoding, segment selectors are usually stored in the high speed segment registers. an instruction need spec- ify only the desired segment r egister and offset in order to address a memory operand. most instructions need not explicitly specify which segment register is used. the correct segment register is automati- cally chosen according to the rules of table 3. these rules follow the way programs are written (see figure 4) as inde- pendent modules that require areas for code and data, a stack, and access to external data areas. special segment override inst ruction prefixes allow the implicit segment register selection rules to be overridden for special cases. the stack, data and extra segments may coincide for simple programs. to access operands not resid- ing in one of the four immediately available segments, a full 32-bit pointer or a new segment selector must be loaded. addressing modes the 80c286 provides a total of eight addressing modes for instructions to specify oper ands. two addressing modes are provided for instructions that operate on register or immedi- ate operands: register operand mode: the operand is located in one of the 8 or 16-bit general registers. immediate operand mode: the operand is included in the instruction. six modes are provided to specify the location of an operand in a memory segment. a memory operand address consists of two 16-bit components: segment selector and offset. the seg- ment selector is supplied by a segment register either implicitly chosen by the addressing mode or explicitly chosen by a seg- ment override prefix. the offset is calculated by summing any combination of the following three address elements: the displacement (an 8 or 16-bit immediate value contained in the instruction) the base (contents of either the bx or bp base registers) the index (contents of either the si or dl index registers) any carry out from the 16-bit addition is ignored. eight-bit displacements are sign extended to 16-bit values. table 3. segment register selection rules memory reference needed segment register used implicit segment selection rule instructions code (cs) automatic with instruction prefetch stack stack (ss) all st ack pushes and pops. any memory reference which uses bp as a base register. local data data (ds) all data references except when relative to stack or string destination external (global) data extra (es) alternate data segment and destination of string operation pointer offset segment 31 16 15 0 operand selected segment memory selected figure 3. two component address code data code data memory cpu code data stack extra segment registers module a module b process stack process data block 1 process data block 2 figure 4. segmented memory helps structure software 80c286 12 combinations of these three address elements define the six memory addressing modes, described below. direct mode: the operand's of fset is contained in the instruction as an 8 or 16-bit displacement element. register indirect mode: t he operand's offset is in one of the registers si, dl, bx or bp. based mode: the operand's offs et is the sum of an 8 or 16-bit displacement and the contents of a base register (bx or bp). indexed mode: the operand's offset is the sum of an 8 or 16- bit displacement and the contents of an index register (si or dl). based indexed mode: the operand 's offset is the sum of the contents of a base register and an index register. based indexed mode with displacement: the operand's offset is the sum of a base register's contents, an index register's contents, and an 8 or 16-bit displacement. data types the 80c286 directly supports the following data types: integer: a signed binary numeric value contained in an 8- bit byte or a 16-bit word. all operations assume a 2's complement representation. signed 32 and 64-bit integers are supported using the 80287 numeric data processor. ordinal: an unsigned binary numeric value contained in an 8-bit byte or 16-bit word. pointer: a 32-bit quantity, co mposed of a segment selector component and an offset component. each com- ponent is a 16-bit word. string: a contiguous sequence of bytes or words. a string may contain from 1 byte to 64k bytes. ascli: a byte representation of alphanumeric and control characters using the ascli standard of character representation. bcd: a byte (unpacked) representation of the decimal digits 0-9. packed a byte (packed) representation of two decimal bcd: digits 0-9 storing one digit in each nibble of the byte. floating a signed 32, 64 or 80-bit real number representa- point: tion. (floating point operands are supported using the 80287 numeric processor extension). figure 5 graphically represents the data types supported by the 80c286. note: supported by 80c286/80c287 numeric data processor configuration signed byte unsigned byte signed word signed double word (note) sign bit sign bit signed quad word (note) sign bit unsigned word binary coded decimal (bcd) ascii string packed bcd pointer floating point (note) sign bit magnitude 70 magnitude 70 msb 15 magnitude msb 14 +1 0 87 0 sign bit 31 +3 +2 16 +1 0 15 0 magnitude magnitude msb msb 63 +6 +7 +5 +4 +3 +2 +1 0 48 47 32 31 16 15 0 magnitude msb 15 +1 0 0 bcd 7 +n 0 digit n bcd 7 +1 0 digit 1 bcd 7 0 0 digit 0 ??? ??? ??? ??? ascii 7 +n 0 character n ascii 7 +1 0 character 1 ascii 7 0 0 character 0 7 +n 0 most significant digit 7 +1 07 0 0 least significant digit byte/word n byte/word 1 byte/word 0 7/15 +n 07/15 +1 07/15 0 0 selector offset 31 +3 16 +1 0 0 exponent magnitude 79 +9 +8 +7 +6 +5 +4 +3 +2 +1 0 0 +1 15 figure 5. 80c286 supported data types 80c286 13 i/o space the i/o space consists of 64k 8-bit ports, 32k 16-bit ports, or a combination of the two. i/o instructions address the i/o space with either an 8-bit port address, specified in the instruction, or a 16-bit port address in the dx register. 8-bit port addresses are zero extended such that a 15 -a 8 are low. i/o port addresses 00f8(h) through 00ff(h) are reserved. interrupts an interrupt transfers execution to a new program location. the old program address (cs:lp) and machine state (flags) are saved on the stack to allow resumption of the interrupted program. interrupts fall into thre e classes: hardware initiated, int instructions, and instruction exceptions. hardware initi- ated interrupts occur in response to an external input and are classified as non-maskable or maskable. programs may cause an interrupt with an int instruction. instruction excep- tions occur when an unusual condition which prevents fur- ther instruction processing is detected while attempting to execute an instruction. the re turn address from an exception will always point to the instruction causing the exception and include any leading instruction prefixes. a table containing up to 256 pointers defines the proper interrupt service routine for each interrupt. interrupts 0-31, some of which are used for instruction exceptions, are reserved. for each interrupt, an 8-bit vector must be sup- plied to the 80c286 which identifies the appropriate table entry. exceptions supply the interrupt vector internally. int instructions contain or imply the vector and allow access to all 256 interrupts. maskable hardware initiated interrupts supply the 8-bit vector to the cpu during an interrupt acknowledge bus sequence. nonmaskable hardware inter- rupts use a predefined internally supplied vector. maskable interrupt (intr) the 80c286 provides a maskable hardware interrupt request pin, intr. software enables this input by setting the interrupt flag bit (if) in the flag word. all 224 user-defined interrupt sources can share this input, yet they can retain separate interrupt handlers. an 8-bit vector read by the cpu during the interrupt acknowledge sequence (discussed in system inter- face section) identifies the source of the interrupt. the processor automatically di sables further maskable inter- rupts internally by resetting the if as part of the response to an interrupt or exception. the saved flag word will reflect the enable status of the processor prior to the interrupt. until the flag word is restored to the flag register, the interrupt flag will be zero unless specifically set. the interrupt return instruc- tion includes restoring the flag word, thereby restoring the original status of if. non-maskable interrupt request (nmi) a non-maskable interrupt input (nmi) is also provided. nmi has higher priority than intr. a typical use of nmi would be to activate a power failure routine. the activation of this input causes an interrupt with an internally supplied vector value of 2. no external interrupt acknowledge sequence is per- formed. while executing the nmi servicing procedure, the 80c286 will service neither further nmi requests, intr requests, nor the processor extension segment overrun interrupt until an interrupt return (lret) instruct ion is executed or the cpu is reset. if nmi occurs while currently servicing an nmi, its presence will be saved for servicing after executing the first iret instruction. if is cleared at the beginning of an nmi interrupt to inhibi t intr interrupts. table 4. interrupt vector assignments function interrupt number related instructions does return address point to instruction causing exception? divide error exception 0 dlv, ldlv yes single step interrupt 1 all nmi interrupt 2 int 2 or nmi pin breakpoint interrupt 3 int 3 into detected overflow exception 4 into no bound range exceeded exception s bound yes invalid opcode exception 6 any undefined opcode yes processor extension not avail able exception 7 esc or wait yes reserved - do not use 8 - 15 processor extension error interrupt 16 esc or wait reserved 17 - 31 user defined 32 - 255 80c286 14 single step interrupt the 80c286 has an internal interrupt that allows programs to execute one instruction at a time. it is called the single step interrupt and is controlled by the single step flag bit (tf) in the flag word. once this bit is set, an internal single step interrupt will occur after the next instruction has been executed. the interrupt clears the tf bit and uses an internally supplied vec- tor of 1. the lret instruction is used to set the tf bit and transfer control to the next instruction to be single stepped. interrupt priorities when simultaneous interrupt requests occur, they are pro- cessed in a fixed order as shown in table 5. interrupt pro- cessing involves saving the flags, return address, and setting cs:lp to point at the first instruction of the interrupt handler. if another enabled interrupt should occur, it is processed before the next instruction of the current interrupt handler is executed. the last interrupt pr ocessed is therefore the first one serviced. initialization and processor reset processor initialization or start up is accomplished by driving the reset input pin high. reset forces the 80c286 to terminate all execution and local bus activity. no instruction or bus activity will occur as long as reset is active. after reset becomes inactive, and an internal processing inter- val elapses, the 80c286 begins execution in real address mode with the instruction at physical location fffff0(h). reset also sets some regist ers to predefined values as shown in table 6. hold must not be active duri ng the time from the leading edge of the initial reset to 34 clks after t he trailing edge of the initial reset of an 80c286 system. machine status word description the machine status word (msw) records when a task switch takes place and controls the operating mode of the 80c286. it is a 16-bit register of whic h the lower four bits are used. one bit places the cpu into protected mode, while the other three bits, as shown in table 7, control the processor exten- sion interface. after reset, th is register contains fff0(h) which places the 80c286 in 80c286 real address mode. the lmsw and smsw instructions can load and store the msw in real address mode. the recommended use of ts, em, and mp is shown in table 8. halt the hlt instruction stops program execution and prevents the cpu from using the local bu s until restarted. either nmi, intr with if = 1, or reset wi ll force the 80c286 out of halt. if interrupted, the saved cs:ip will point to the next instruc- tion after the hlt. table 5. interrupt processing order order interrupt 1 instruction exception 2 single step 3nmi 4 processor extension segment overrun 5intr 6 int instruction table 6. 80c286 initial register state after reset flag word 0002(h) machine status word fff0(h) instruction pointer fff0(h) code segment f000(h) data segment 0000(h) extra segment 0000(h) stack segment 0000(h) table 7. msw bit functions bit position name function 0 pe protected mode enable places the 80c286 into protected mode and cannot be cleared except by reset. 1 mp monitor processor extension allows wait instructions to cause a processor exten- sion not present exception (number 7). 2 em emulate processor extension causes a processor extension not present excep- tion (number 7) on esc instructions to al- low emulating a pr ocessor extension. 3 ts task switched indicates the next instruc- tion using a processo r extension will cause exception 7, allowing software to test whether the current processor exten- sion context belongs to the current task. 80c286 15 80c286 real address mode the 80c286 executes a fully upward-compatible superset of the 80c86 instruction set in real address mode. in real address mode the 80c286 is object code compatible with 80c86 and 80c88 software. the real address mode archi- tecture (registers and addressing modes) is exactly as described in the 80c286 base architecture section of this functional description. memory size physical memory is a contiguous array of up to 1,048,576 bytes (one megabyte) addressed by pins a 0 through a 19 and bhe . a 20 through a 23 should be ignored. memory addressing in real address mode physical memory is a contiguous array of up to 1,048,576 bytes (one megabyte) addressed by pin a 0 through a 19 and bhe . address bits a 20 -a 23 may not always be zero in real mode. a 20 -a 23 should not be used by the system while the 80c286 is operating in real mode. the selector portion of a pointer is interpreted as the upper 16-bits of a 20-bit segment address. the lower four bits of the 20-bit segment address are always zero. segment addresses, therefore, begin on multiples of 16 bytes. see figure 6 for a graphic representation of address information. all segments in real address mode are 64k bytes in size and may be read, written, or executed. an exception or interrupt can occur if data operands or instructions attempt to wrap around the end of a segment (e.g. a word with its low order byte at offset ffff(h) and it s high order byte at offset 0000(h)). if, in real address mode, the information contained in a segment does not use the full 64k bytes, the unused end of the segment may be overlaid by another segment to reduce physical memory requirements. table 8. recommended msw encodings for processor extension control ts mp em recommended use instruction causing exception 7 0 0 0 initial encoding after reset. 80c286 operation is identical to 80c86/88. none 0 0 1 no processor extension is available. software will emulate its function. esc 1 0 1 no processor extension is available. software will emulate its function. the current processor extension c ontext may belong to another task. esc 0 1 0 a processor extension exists. none 1 1 0 a processor extension exists. the cu rrent processor extension context may belong to another task. the exception 7 on wait allows software to test for an error pending from a previous processor extension operation. esc or wait table 9. real address mode addressing interrupts function interrupt number related instructions return address before instruction interrupt table limit too small exception 8 int vector is not within table limit yes processor extensi on segment overrun interrupt 9 esc with memory operand extending beyond offset ffff(h) no segment overrun exception 13 word memory reference with offset = ffff(h) or an attempt to execute past the end of a segment yes 0000 offset offset address 0000 segment selector adder 19 0 0 15 15 0 20-bit physical memory address segment address figure 6. 80c286 real address mode address calculation 80c286 16 reserved memory locations the 80c286 reserves two fixed areas of memory in real address mode (see figure 7); system initialization area and interrupt table area. locations from addresses ffff0(h) through fffff(h) are re served for system initialization. initial execution begins at location ffff0(h). locations 00000(h) through 003ff(h) are reserved for interrupt vectors. interrupts table 9 shows the interrupt ve ctors reserved for exceptions and interrupts which indicate an addressing error. the exceptions leave the cpu in the state existing before attempting to execute the failing instruction (except for push, pop, pusha, or popa). refer to the next section on protected mode initialization for a discussion on exception 8. protected mode initialization to prepare the 80c286 for prot ected mode, the lidt instruc- tion is used to load the 24-bit interrupt table base and 16-bit limit for the protected mode interrupt table. this instruction can also set a base and limit for the interrupt vector table in real address mode. after reset, the interrupt table base is ini- tialized to 000000(h) and its size set to 03ff(h). these val- ues are compatible with 80c86 and 80c88 software. lidt should only be executed in pr eparation for protected mode. shutdown shutdown occurs when a severe error is detected that prevents further instruction processing by the cpu. shutdown and halt are externally signalled via a halt bus operation. they can be distinguished by a 1 high for halt and a 1 low for shutdown. in real address mode, shutdown can occur under two conditions: exceptions 8 or 13 happe n and the idt limit does not include the interrupt vector. a call int or push instruct ion attempts to wrap around the stack segment when sp is not even. an nmi input can bring the cpu out of shutdown if the idt limit is at least 000f(h) and sp is greater than 0005(h), oth- erwise shutdown can only be exited via th e reset input. 3h reset bootstrap program jump interrupt pointer for vector 255 interrupt pointer for vector 1 interrupt pointer for vector 0 fffffh ffff0h 3ffh 3fch 7h 4h 0h ? ? ? ? ? ? initial cs:ip value is f000:fff0 figure 7. 80c286 real address mode initially reserved memory locations 80c286 17 protected virtual address mode the 80c286 executes a fully upward-compatible superset of the 80c86 instruction set in protected virtual address mode (protected mode). protected mode also provides memory management and protection me chanisms and associated instructions. the 80c286 enters protected virtual address mode from real address mode by setting the pe (protection enable) bit of the machine status word with the load machine status word (lmsw) instruction. protected mode offers extended physi- cal and virtual memory address space, memory protection mechanisms, and new operations to support operating sys- tems and virtual memory. all registers, instructions, and addressing modes described in the 80c286 base architecture section of this functional description remain the same. programs for the 80c86, 80c88, and real address mode 80c286 can be run in pro- tected mode; however, embedded constants for segment selectors are different. memory size the protected mode 80c286 provides a 1 gigabyte virtual address space per task mapped into a 16 megabyte physical address space defined by the address pins a 23 -a 0 and bhe . the virtual address space may be larger than the physical address space since any use of an address that does not map to a physical memory location will cause a restartable exception. memory addressing as in real address mode, protected mode uses 32-bit point- ers, consisting of 16-bit sele ctor and offset components. the selector, however, specifies an index into a memory resident table rather than the upper 16-bits of a real memory address. the 24-bit base address of t he desired segment is obtained from the tables in memory. the 16-bit offset is added to the segment base address to form the physical address as shown in figure 8. the tables are automatically referenced by the cpu whenever a segment register is loaded with a selector. all 80c286 instructions which load a segment reg- ister will reference the memory based tables without addi- tional software. the memory based tables contain 8 byte values called descriptors. descriptors descriptors define the use of memory. special types of descriptors also define new func tions for transfer of control and task switching. the 80c286 has segment descriptors for code, stack and data segments, and system control descrip- tors for special system data segments and control transfer operations. descriptor accesses are performed as locked bus operations to assure descriptor integrity in multi-proces- sor systems. code and data segment descriptors (s = 1) besides segment base addresses, code and data descriptors contain other segment attributes including segment size (1 to 64k bytes), access rights (read only, read/write, execute only, and execute/read), and presence in memory (for virtual mem- ory systems) (see table 10). any segment usage violating a segment attribute indicated by the segment descriptor will pre- vent the memory cycle and caus e an exception or interrupt. code and data (including stack data) are stored in two types of segments: code segments and data segments. both types are identified and defined by segment descriptors (s = 1). code segments are identified by the executable (e) bit set to 1 in the descriptor access rights byte. the access rights byte of both code and data segment descriptor types have three fields in common: present (p) bit, descriptor privilege level (dpl), and accessed (a) bit. if p = 0, any attempted use of this segment will cause a not-present exception. dpl speci- fies the privilege level of t he segment descriptor. dpl con- trols when the descriptor may be used by a task (refer to privilege discussion below). the a bit shows whether the segment has been previously ac cessed for usage profiling, a necessity for virtual memory systems. the cpu will always set this bit when a ccessing the descriptor. physical address adder memory operand segment descriptor segment base address pointer selector offset physical memory segment segment description table 0 23 31 16 15 0 cpu figure 8. protected mode memory addressing reserved ? access rights byte pdplstype a base 23 - 16 base 15 - 0 limit 15 - 0 15 707 7 80 0 +6 +4 +2 0 +7 +5 +3 +1 ? must be set to 0 for compatibility with future upgrades figure 9. code or data segment descriptor 80c286 18 table 10. code and data segment descriptor formats - access rights byte definition bit position name function 7 present (p) p = 1 segment is mapped into physical memory. p = 0 no mapping to physical memory exits, base and limit are not used. 6 - 5 descriptor privilege level (dpl) segment privilege attribute used in privilege tests. 4 segment descriptor (s) s = 1 code or data (includes stacks) segment descriptor s = 0 system segment descriptor or gate descriptor 3 executable (e) e = 0 data segment descriptor type is: if data segment (s = 1, e = 0) 2 expansion direction (ed) ed = 0 expand up segment, offsets must be limit. ed = 1 expand down segment, offsets must be > limit. 1 writable (w) w = 0 data segment may not be written into. w = 1 data segment may be written into. type field definition 3 executable (e) e = 1 code segment descriptor type is: if code segment (s = 1, e = 1) 2 conforming (c) c = 1 code segment may only be executed when cpl dpl and cpl remains unchanged. 1 readable (r) r = 0 code segment may not be read. r = 1 code segment may be read. 0 accessed (a) a = 0 segment has not been accessed. a = 1 segment selector has been loaded into segment register or used by selector test instructions. 80c286 19 data segments (s = 1, e = 0) may be either read-only or read- write as controlled by the w bit of the access rights byte. read-only (w = 0) data segments may not be written into. data segments may grow in two directions, as determined by the expansion direction (ed) bit: upwards (ed = 0) for data segments, and downwards (ed = 1) for a segment containing a stack. the limit field for a data segment descriptor is inter- preted differently depending on the ed bit (see table 10). a code segment (s = 1, e = 1) may be execute-only or exe- cute/read as determined by the readable (r) bit. code seg- ments may never be written into and execute-only code segments (r = 0) may not be read. a code segment may also have an attribute called conforming (c). a conforming code segment may be shared by programs that execute at different privilege levels. the dpl of a conforming code seg- ment defines the range of privilege levels at which the seg- ment may be executed (refer to privilege discussion below). the limit field identifies the last byte of a code segment. system segment descriptors (s = 0, type = 1-3) in addition to code and data segment descriptors, the pro- tected mode 80c286 defines system segment descriptors. these descriptors define s pecial system data segments which contain a table of descriptors (local descriptor table descriptor) or segments which contain the execution state of a task (task state segment descriptor). table 11 gives the formats for the special system data seg- ment descriptors. the descriptors contain a 24-bit base address of the segment and a 16-bit limit. the access byte defines the type of descriptor, its state and privilege level. the descriptor contents are valid and the segment is in phys- ical memory if p = 1. if p = 0, the segment is not valid. the dpl field is only used in task state segment descriptors and indicates the privilege level at which the descriptor may be used (see privilege). since the local descriptor table descriptor may only be used by a special privileged instruc- tion, the dpl field is not used. bit 4 of the access byte is 0 to indicate that it is a system control descriptor. the type field specifies the descri ptor type as indicated in table 11. gate descriptors (s = 0, type = 4-7) gates are used to control acce ss to entry points within the target code segment. the ga te descriptors are call gates, task gates, interrupt gates and trap gates. gates provide a level of indirection between the source and destination of the control transfer. this indirect ion allows the cpu to automati- cally perform protection checks and control entry point of the destination. call gates are used to change privilege levels (see privilege), task gates are used to perform a task switch, and interrupt and trap gates are used to specify interrupt ser- vice routines. the interrupt gate disables interrupts (resets if) while the trap gate does not. table 12 shows the format of the gate descriptors. the descriptor contains a destination pointer that points to the descriptor of the target segment and the entry point offset. the destination selector in an interrupt gate, trap gate, and call gate must refer to a code segment descriptor. these gate descriptors contain the entry point to prevent a program from constructing and using an illegal entry point. task gates may only refer to a task state segment. since task gates invoke a task switch, the destination offset is not used in the task gate. exception 13 is generated when the gate is used if a destina- tion selector does not refer to the correct descriptor type. the word count field is used in the call gate descriptor to indicate the number of parameters (0-31 words) to be automatically copied from the caller?s stack to the stack of the called routine when a control transfer changes privilege levels. the word count field is not used by any other gate descriptor. the access byte format is the same for all descriptors. p = 1 indicates that the gate contents are valid. p = 0 indicates the contents are not valid and causes exception 11 if referenced. dpl is the descriptor privilege level and specifies when this descriptor may be used by a task (refer to privilege discus- sion below). bit 4 must equal 0 to indicate a system control descriptor. the type field specifies the descriptor type as indicated in table 12. reserved ? pdpl0 type base 23 - 16 base 15 - 0 limit 15 - 0 15 707 7 80 0 +6 +4 +2 0 +7 +5 +3 +1 ? must be set to 0 for compatibility with future upgrades figure 10. system segment descriptor table 11. system segment descriptor format fields name value description type 1 available task state segment (tss) 2 local descriptor table 3 busy task state segment (tss) p 0 descriptor contents are not valid 1 descriptor contents are valid dpl 0-3 descriptor privilege level base 24-bit number base address of special system data segment in real memory limit 16-bit number offset of last byte in segment 80c286 20 segment descriptor cache registers a segment descriptor cache register is assigned to each of the four segment registers (cs, ss, ds, es). segment descriptors are automatically loaded (cached) into a seg- ment descriptor cache regist er (figure 12) whenever the associated segment register is loaded with a selector. only segment descriptors may be loaded into segment descriptor cache regi sters. once loaded, all references to that segment of memory use the cached descriptor informa- tion instead of reaccessing the descriptor. the descriptor cache registers are not visible to programs. no instructions exist to store their contents. they only change when a seg- ment register is loaded. selector fields a protected mode selector has three fields: descriptor entry index, local or global descriptor table indicator (t i ), and selec- tor privilege (rpl) as shown in figure 13. these fields select one of two memory based tables of descriptors, select the appropriate table entry and allow high-speed testing of the selector's privilege attribute (refer to privilege discussion below). local and global descriptor tables two tables of descriptors, called descriptor tables, contain all descriptors accessible by a task at any given time. a descriptor table is a linear array of up to 8192 descriptors. the upper 13 bits of the selector value are an index into a descriptor table. each table has a 24-bit base register to locate the descriptor table in physical memory and a 16-bit limit register that confine descriptor access to the defined limits of the table as shown in figure 14. a restartable exception (13) will occur if an attempt is made to reference a descriptor outside the table limits. one table, called the global descriptor table (gdt), contains descriptors available to all tasks. the other table, called the local descriptor table (ldt), contains descriptors that can be private to a task. each task may have its own private ldt. the gdt may contain all descriptor types except interrupt and trap descriptors. the ld t may contain only segment, task gate, and call gate descriptors. a segment cannot be accessed by a task if its segment descriptor does not exist in either descriptor table at the time of access. table 12. gate descriptor format field name value description type 4 call gate 5 task gate 6 interrupt gate 7 trap gate p 0 descriptor contents are not valid 1 descriptor contents are valid dpl 0 - 3 descrip tor privilege level word count 0 - 31 number of words to copy from callers stack to called procedures stack. only used with call gate. destination selector 16-bit selector selector to the target code segment (call, interrupt or selector trap gate). selector to the target task state seg- ment (task gate). destination offset 16-bit offset entry point within the target code seg- ment reserved ? pdpl0 type destination selector 15 - 0 destination offset 15 - 0 15 707 7 80 0 +6 +4 +2 0 +7 +5 +3 +1 ? must be set to 0 for compatibility with future upgrades xx x xx word count 4 - 0 figure 11. gate descriptor bits name function 1 - 0 requested privilege level (rpl) indicates selector privilege level desired 2 table indicator (ti) ti = 0 use global descrip- tor table (gdt) ti = 1 use local descriptor table (ldt) 15 - 3 index select descriptor entry in table figure 13. selector fields program visible segment selectors cs ds ss es 15 0 segment registers (loaded by program) segment size segment physical base address access rights program invisible 47 40 39 16 15 0 segment descriptor cache registers (automatically loaded by cpu) figure 12. descriptor cache registers index rpl ti 15 8 7 2 1 0 selector 80c286 21 the lgdt and lldt instructions load the base and limit of the global and local descriptor tables. lgdt and lldt are privileged, i.e. they may only be executed by trusted pro- grams operating at level 0. t he lgdt instruction loads a six byte field containing the 16-bit table limit and 24-bit physical base address of the global descriptor table as shown in fig- ure 15. the ldt instruction loads a selector which refers to a local descriptor table descriptor containing the base address and limit for an ldt, as shown in table 11. interrupt descr iptor table the protected mode 80c286 has a third descriptor table, called the interrupt descriptor table (idt) (see figure 16), used to define up to 256 interrupts. it may contain only task gates, interrupt gates and trap gates. the idt (interrupt descriptor table) has a 24-bit physical base and 16-bit limit register in the cpu. the privileged lldt instruction loads these registers with a six byte value of identical form to that of the lgdt instruction (see figure 16 and protected mode lnitialization). references to idt entries are made via int instructions, exter- nal interrupt vectors, or exceptions. the idt must be at least 256 bytes in size to allocate space for all reserved interrupts. privilege the 80c286 has a four-level hierarchical privilege system which controls the use of priv ileged instructions and access to descriptors (and their associated segments) within a task. four-level privilege, as shown in figure 17, is an extension of the users/supervisor mode commonly found in minicom- puters. the privilege levels are numbered 0 through 3. level 0 is the most privileged level. privilege levels provide protec- tion within a task. (tasks are isolated by providing private ldt?s for each task.) operating system routines, interrupt handlers, and other system so ftware can be included and protected within the virtual add ress space of each task using the four levels of privilege. each task in the system has a separate stack for each of its privilege levels. tasks, descriptors, and selectors have a privilege level attribute that determines whether the descriptor may be used. task privilege affects the use of instructions and descriptors. descriptor and selector privilege only affect access to the descriptor. cpu gdt limit gdt base 24-bit phys ad ldt descr selector ldt limit ldt base 24-bit phys ad program invisible (automatically loaded from ldt descr within gdt) gdt current ldt increasing memory address memory ldt 1 ldt n 15 0 0 0 15 23 23 15 figure 14. local and global descriptor table definition reserved ? base 15 - 0 limit 15 - 0 15 707 7 80 0 +4 +2 0 +5 +3 +1 ? must be set to 0 for compatibility with future upgrades base 23 - 16 figure 15. global descriptor table and interrupt descrlptor table data type idt limit idt base interrupt descriptor tab le memory 0 15 23 0 gate for interrupt #n cpu gate for interrupt #1 gate for interrupt #n-1 gate for interrupt #0 increasing memory address (idt) figure 16. interrupt descriptor table definition applications os extensions system services kernal pl = 0 most privileged cpu enforced software interfaces high speed operating system interface pl = 1 pl = 2 pl = 3 note: pl becomes numerically lower as privilege level increases. figure 17. hierarchical privilege levels 80c286 22 task privilege a task always executes at one of the four privilege levels. the task privilege level at any specific instant is called the current privilege level (cpl) and is defined by the lower two bits of the cs register. cpl cannot change during execution in a single code segment. a task's cpl may only be changed by control transfers through gate descriptors to a new code segment (s ee control transfer). tasks begin exe- cuting at the cpl value specified by the code segment selector within tss when the task is initiated via a task switch operation (see figure 18). a task executing at level 0 can access all data segments defined in the gdt and the task's ldt and is considered the most trusted level. a task executing a level 3 has the most restricted access to data and is considered the least trusted level. descriptor privilege descriptor privilege is specif ied by the descriptor privilege level (dpl) field of the descriptor access byte. dpl specifies the least trusted task privilege level (cpl) at which a task may access the descriptor. descript ors with dpl = 0 are the most protected. only task s executing at privilege level 0 (cpl = 0) may access them. descriptors with dpl = 3 are the least pro- tected (i.e. have the least restricted access) since tasks can access them when cpl = 0, 1, 2, or 3). this rule applies to all descriptors, except ldt descriptors. selector privilege selector privilege is specifi ed by the requested privilege level (rpl) field in the least significant two bits of a selector. selector rpl may establish a less trusted privilege level than the current privilege level for the use of a selector. this level is called the task's effective privilege level (epl). rpl can only reduce the scope of a task's access to data with this selector. a task's effective privilege is the numeric maxi- mum of rpl and cpl. a selector with rpl = 0 imposes no additional restriction on its us e while a selector with rpl = 3 can only refer to segments at privilege level 3 regardless of the task's cpl. rpl is generally used to verify that pointer parameters passed to a more trusted procedure are not allowed to use data at a more privileged level than the caller (refer to pointer testing instructions). descriptor access and privilege validation determining the ability of a task to access a segment involves the type of segment to be accessed, the instruction used, the type of descriptor used and cpl, rpl, and dpl. the two basic types of segment accesses are control trans- fer (selectors loaded into cs) and data (selectors loaded into ds, es or ss). data segment access instructions that load selectors into ds and es must refer to a data segment descriptor or readable code segment descriptor. the cpl of the ta sk and the rpl of the selector must be the same as or more privileged (numerically equal to or lower than) than the descriptor dpl. in general, a task can only access data segments at the same or less privi- leged levels than the cpl or rpl (whichever is numerically higher) to prevent a program from accessing data it cannot be trusted to use. an exception to the rule is a readable conforming code seg- ment. this type of code segment can be read from any privi- lege level. if the privilege checks fail (e.g. dpl is numerically less than the maximum of cpl and rpl) or an incorrect type of descriptor is referenced (e.g. gate descriptor or execute only code segment) exception 13 oc curs. if the segment is not present, exception 11 is generated. instructions that lo ad selectors into ss must refer to data segment descriptors for writable data segments. the descriptor privilege (dpl) an d rpl must equal cpl. all other descriptor types or a privilege level violation will cause exception 13. a not present fault causes exception 12. table 13. descrlptor types used for control transfer control transfer types operation types descriptor referenced descriptor table intersegment within the same privilege levels jmp, call, ret, lret (note 4) code segment gdt/ldt intersegment to the same or hi gher privilege level interrupt within task may change cpl call call gate gdt/ldt interrupt instruction, exception external interrupt trap or interrupt gate ldt intersegment to a lower privilege level (changes ta sk cpl) ret, iret (note 4) code segment gdt/ldt task switch call, jmp task state segment gdt call, jmp task gate gdt/ldt lret (note 5) interrupt instruction, exception external interrupt task gate idt notes: 4. nt (nested task bit of flag word) = 0 5. nt (nested task bit of flag word) = 1 80c286 23 control transfer four types of control transfer can occur when a selector is loaded into cs by a control transfer operation (see table 13). each transfer type can only occur if the operation which loaded the selector references the correct descriptor type. any violation of these descriptor usage rules (e.g. jmp through a call gate or ret to a task state segment) will cause exception 13. the ability to reference a descriptor for control transfer is also subject to rules of privilege. a call or jump instruc- tion may only reference a code segment descriptor with dpl equal to the task cpl or a conforming segment with dpl of equal or greater privilege than cpl. the rpl of the selector used to reference the code descriptor must have as much privilege as cpl. ret and iret instructions may only reference code seg- ment descriptors with descriptor privilege equal to or less privileged than the task cpl. t he selector loaded into cs is the return address from the stack. after the return, the selec- tor rpl is the task's new cpl. if cpl changes, the old stack pointer is popped after the return address. when a jmp or call references a task state segment descriptor, the descriptor dpl must be the same or less priv- ileged than the task's cpl. reference to a valid task state segment descriptor causes a ta sk switch (see task switch operation). reference to a task state segment descriptor at a more privileged level than the task's cpl generates excep- tion 13. when an instruction or interrupt references a gate descriptor, the gate dpl must have the same or less privilege than the task cpl. if dpl is at a more privileged level than cpl, exception 13 occurs. if the destination selector contained in the gate references a code segment descriptor, the code segment descriptor dpl must be the same or more privi- leged than the task cpl. if not, exception 13 is issued. after the control transfer, the code segment descriptors dpl is the task's new cpl. if the destination selector in the gate refer- ences a task state segment, a task switch is automatically performed (see task switch operation). the privilege rules on control transfer require: jmp or call direct to a code segment (code segment descriptor) can only be a c onforming segment with dpl of equal or greater privilege than cpl or a non-conforming segment at the same privilege level. interrupts within the task, or calls that may change privilege levels, can only transfer control through a gate at the same or a less privileged level than cpl to a code segment at the same or more privileged level than cpl. return instructions that don't switch tasks can only return control to a code segment at the same or less privileged level. task switch can be performed by a call, jump or interrupt which references either a task gate or task state segment at the same or less privileged level. privilege level changes any control transfer that changes cpl within the task, causes a change of stacks as par t of the operation. initial values of ss:sp for privilege levels 0, 1, and 2 are kept in the task state segment (refer to task switch operation). during a jmp or call control transfer, the new stack pointer is loaded into the ss and sp registers and the previous stack pointer is pushed onto the new stack. when returning to the original privilege level, its stack is restored as part of the ret or iret instruction operation. for subroutine calls that pass parameters on the stack and cross privilege levels, a fixed number of words, as specified in the gate, are copied from the previous stack to the current stack. the inter-segment ret instruction with a stack adjust- ment value will correctly restore the previous stack pointer upon return. protection the 80c286 includes mechanisms to protect critical instruc- tions that effect the cpu exec ution state (e.g. hlt) and code or data segments from improper usage. these protection mechanisms are grouped into three forms: restricted usage of segments (e.g. no write allowed to read-only data segments). the only segments available for use are defined by descriptors in the local descriptor table (ldt) and global descriptor table (gdt). restricted access to segments via the rules of privilege and descriptor usage. privileged instructions or operations that may only be exe- cuted at certain privilege levels as determined by the cpl and i/o privilege level (lopl). the lopl is defined by bits 14 and 13 of the flag word. these checks are performed for all instructions and can be split into three categories: segment load checks (table 14), operand reference checks (table 15), and privileged instruc- tion checks (table 16). any violation of the rules shown will result in an exception. a not-present exception related to the stack segment causes exception 12. table 14. segment register load checks error description exception number descriptor table limit exceeded 13 segment descriptor not-present 11 or 12 privilege rules violated 13 invalid descriptor/segment type segment register load: - read only data segment load to ss - special control descriptor load to ds, es, ss - execute only segment load to ds, es, ss - data segment load to cs - read/execute code segment load ss 13 80c286 24 the lret and popf instructio ns do not perform some of their defined functions if cpl is not of sufficient privilege (numerically small enough). precisely these are: the if bit is not changed if cpl is greater than iopl. the lopl field of the flag word is not changed if cpl is greater than 0. no exceptions or other indication are given when these con- ditions occur. exceptions the 80c286 detects several types of exceptions and inter- rupts in protected mode (see table 17). most are restartable after the exceptional condition is removed. interrupt handlers for most exceptions can read an error code, pushed on the stack after the return address, that identifies the selector involved (0 if none). the return address normally points to the failing instruction including all leading prefixes. for a pro- cessor extension segment overrun exception, the return address will not point at the esc instruction that caused the exception; however, the processor extension registers may contain the address of the failing instruction. these exceptions indicate a violation to privilege rules or usage rules has occurred. restart is generally not attempted under those conditions. all these checks are performed for all instructions and can be split into three categories: segment load checks (table 14), operand reference checks (table 15), and privileged instruction checks (table 16). any violation of the rules shown will result in an exception. a not-present exception causes exception 11 or 12 and is restartable. special operations task switch operation the 80c286 provides a built-in task switch operation which saves the entire 80c286 execution state (registers, address space, and a link to the previous task), loads a new execution state, and commences execution in the new task. like gates, the task switch operation is invoked by executing an inter-seg- ment jmp or call instruction which refers to a task state segment (tss) or task gate descriptor in the gdt or ldt. an int instruction, exception, or external interrupt may also invoke the task switch operation by selecting a task gate descriptor in the associated idt descriptor entry. the tss descriptor points at a segment (see figure 18) con- taining the entire 80c286 execution state while a task gate descriptor contains a tss selector. the limit field of the descriptor must be greater than 002b(h). each task must have a tss a ssociated with it. the current tss is identified by a special register in the 80c286 called the task register (tr). this register contains a selector referring to the task state segment descriptor that defines the current tss. a hidden base and limit register associated with tr are loaded whenever tr is loaded with a new selec- tor. the iret instruction is used to return control to the task that called the current task or was interrupted. bit 14 in the flag register is called the nested task (nt) bit. it controls the table 15. operand reference checks error description exception number write into code segment 13 read from execute-only code segment 13 write to read-only data segment 13 segment limit exceeded (see note) 12 or 13 note: carry out in offset calculations is ignored. table 16. privileged instruction checks error description exception number cpl 0 when executing the following instructions: lidt, lldt, lgdt, ltr, lmsw, cts, hlt 13 cpt > iopl when executing the following instructions: ins, in, outs, out, sti, cli, lock 13 table 17. protected mode exceptions interrupt vector function return address at falling instruction? always restartable? error code on stack? 8 double exception detected yes no (note 7) yes 9 processor extension segment overrun no no (note 7) no 10 invalid task state segment yes yes yes 11 segment not present yes yes yes 12 stack segment overrun or stack se gment not present yes yes (note 6) yes 13 general protection yes no (note 7) yes notes: 6. when a pusha or popa instruction attempts to wrap around t he stack segment, the machine state after the exception will not be restartable because stack segment wrap around is not per mitted. this condition is id entified by the value of t he saved sp being either 0000 (h), 0001(h), fffe(h), or ffff(h). 7. these exceptions indicate a violation to privilege rules or usage rules has occurred. restart is generally not attempted unde r those conditions. 80c286 25 function of the iret instruction. if nt = 0, the iret instruc- tion performs the regular current task by popping values off the stack; when nt = 1, iret performs a task switch opera- tion back to the previous task. when a call, jmp, or int inst ruction initiates a task switch, the old (except for case of jmp) and new tss will be marked busy and the back link field of the new tss set to the old tss selector. the nt bit of the new task is set by call or int initiated task switches. an interrupt that does not cause a task switch will clear nt. nt may also be set or cleared by popf or iret instructions. the task state segment is marked busy by changing the descriptor type field from type 1 to type 3. use of a selec- tor that references a busy task state segment causes exception 13. processor extension context switching the context of a processor extension is not changed by the task switch operation. a processor extension context need only be changed when a different task attempts to use the processor extension (which still contains the context of a pre- vious task). the 80c286 detects the first use of a processor extension after a task switch by causing the processor exten- sion not present exception (7). the interrupt handler may then decide whether a contex t change is necessary. whenever the 80c286 switches tasks, it sets the task switched (ts) bit of the msw. ts indicates that a proces- sor extension context may belong to a different task than the current one. the processor extension not present exception (7) will occur when attempting to execute an esc or wait instruction if ts = 1 and a processor extension is present (mp = 1 in msw). pointer testing instructions the 80c286 provides several instructions to speed pointer testing and consistency checks for maintaining system integ- rity (see table 18). these instructions use the memory man- agement hardware to verify that a selector value refers to an appropriate segment without risking an exception. a condition flag (zf) indicates whether use of the selector or segment will cause an exception. double fault and shutdown if two separate exceptions are detected during a single instruction execution, the 80c 286 performs the double fault exception (8). if an exception occurs during processing of the double fault exception, the 80c286 will enter shutdown. during shutdown no further inst ructions or exceptions are processed. either nmi (cpu remains in protected mode) or reset (cpu exits protected mode) can force the 80c286 out of shutdown. shutdown is externally signalled via a halt bus operation with a 1 low. protected mode lnitialization the 80c286 initially executes in real address mode after reset. to allow initialization c ode to be placed at the top of physical memory. a 23 - 20 will be high when the 80c286 performs memory references rela tive to the cs register until cs is changed. a 23 - 20 will be zero for references to the ds, es, or ss segments. changing cs in real address mode will force a 23 - 20 low whenever cs is used again. the initial cs:lp value of f000:fff0 provides 64k bytes of code space for initialization code without changing cs. protected mode operation requ ires several registers to be initialized. the gdt and idt base registers must refer to a valid gdt and idt. after executing the lmsw instruction to set pe, the 80c286 must immediately execute an intraseg- ment jmp instruction to clear the instruction queue of instructions decoded in real address mode. to force the 80c286 cpu regist ers to match the initial pro- tected mode state assumed by software, execute a jmp instruction with a selector referring to the initial tss used in the system. this will load the task register, local descriptor table register, segment registers and initial general register state. the tr should point at a valid tss since any task switch operation involves sa ving the current task state. table 18. 80c286 pointer test instructions instruction operands function arpl selector, register adjust requested privilege level: adjusts the rpl of the selector to the numeric maximum of current selector rpl value and the rpl value in the register. set zero flag if selector rpl was changed by arpl. verr selector verify for read: sets the zero flag if t he segment referred to by the selector can be read. verw selector verify for write: sets the zero flag if the segment referred to by the selector can be written. lsl register, selector load segment limit: reads the segment limit into the register if privilege rules and descriptor type allow. set zero flag if successful. lar register, selector load access rights: reads the descrip tor access rights byte into the register if privilege rules al- low. set zero flag if successful. 80c286 26 system interface the 80c286 system interface appears in two forms: a local bus and a system bus. the local bus consists of address, data, status, and control signals at the pins of the cpu. a sys- tem bus is any buffered version of the local bus. a system bus may also differ from the local bus in terms of coding of status and control lines and/or timing and loading of signals. bus interface si gnals and timing the 80c286 microsystems local bus interfaces the 80c286 to local memory and i/o components. the interface has 24 address lines, 16 data lines, and 8 status and control signals. the 80c286 cpu, 82c284 clock generator, 82c288 bus controller, 82289 bus arbiter, 82c86h/87h transceivers, and 82c82/83h latches provide a buffered and decoded system bus interface. the 82c284 generates the system clock and limit base 0 15 23 0 cpu task register type description 1 an available task state segment. may be used as the destination of a task switch operation. 3 a busy task state segment. can- not be used as the destination of a task switch. system segment descriptor tr reserved p d p l 0 type base 15 - 0 limit 15 - 0 base 23 - 16 task ldt selector ds selector ss selector cs selector es selector di si bp sp bx dx cx ax flag word ip (entry point) ss for cpl 2 sp for cpl 2 ss for cpl 1 sp for cpl 1 ss for cpl 0 sp for cpl 0 back link selector to tss 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 current task state initial stacks for cpl 0, 1, 2 byte offset task state segment program invisible 15 0 15 0 p description 1 base and limit fields are valid. 0 segment is not present in mem- ory, base and limit are not de- fined. figure 18. task state segment and tss registers 80c286 27 synchronizes ready and reset. the 82c288 converts bus operation status encoded by the 80c286 into command and bus control signals. the 82289 bus arbiter generates multi- bus? bus arbitration signals . these components can pro- vide the critical timing required for most system bus interfaces including the multibus. bus hold circuitry to avoid high current conditions caused by floating inputs to cmos devices, and to eliminate the need for pull-up/down resistors, ?bus-hold? circuitry has been used on the 80c286 pins 4-6, 36-51 and 66-68 (see figure 19a and 19b). the circuit shown in figure 19a will maintain the last valid logic state if no driving source is present (i.e. an unconnected pin or a driving source which g oes to a high impedance state). the circuit shown in figure 19b will maintain a high imped- ance logic one state if no driving source is present. to over- drive the ?bus-hold? circuits, an external driver must be capable of sinking or sourcing approximately 400 microamps at valid input voltage levels. since this ?bus-hold? circuitry is active and not a ?resistive? type element, the associated power supply current is negligible, and power dissipation is significantly reduced when compared to the use of passive pull-up resistors. physical memory and i/o interface a maximum of 16 megabytes of physical memory can be addressed in protected mode. one megabyte can be addressed in real address mode . memory is accessible as bytes or words. words consist of any two consecutive bytes addressed with the least signific ant byte stored in the lowest address. byte transfers occur on either half of the 16-bit local data bus. even bytes are accessed over d 7-0 while odd bytes are transferred over d 15-8 . even addressed words are trans- ferred over d 15-0 in one bus cycle, while odd addressed word require two bus operations. the first transfers data on d 15-8 , and the second transfers data on d 7-0 . both byte data trans- fers occur automatically, transparent to software. two bus signals, a 0 and bhe , control transfers over the lower and upper halves of the data bus. even address byte transfers are indicated by a 0 low and bhe high. odd address byte transfers are indicated by a 0 hlgh and bhe low. both a 0 and bhe are low for even address word transfers. the i/o address space contains 64k addresses in both modes. the i/o space is accessible as either bytes or words, as is memory. byte wide peripheral devices may be attached to either the upper or lower byte of the data bus. byte-wide i/o devices attached to the upper data byte (d 15-8 ) are accessed with odd i/o addresses. devices on the lower data byte are accessed with even i/o addresses. an interrupt controller such as intersil's 82c59a must be connected to the lower data byte (d 7-0 ) for proper return of the interrupt vector. bus operation the 80c286 uses a double frequency system clock (clk input) to control bus timing. all signals on the local bus are measured relative to the syst em clk input. the cpu divides the system clock by 2 to produce the internal processor clock, which determines bus state. each processor clock is composed of two system clock cycles named phase 1 and phase 2. the 82c284 clock generator output (pclk) identi- fies the next phase of the processor clock. (see figure 20.) six types of bus operations are supported; memory read, memory write, i/o read, i/o write, interrupt acknowledge, and halt/shutdown. data can be transferred at a maximum rate of one word per two processor clock cycles. the 80c286 bus has three basic states: idle (t i ), send status (t s ), and perform command (t c ). the 80c286 cpu also has a fourth local bus state called hold (t h ). t h indicates that the 80c286 has surrendered control of the local bus to another bus master in response to a hold request. each bus state is one processor clock long. figure 21 shows the four 80c286 local bus st ates and allowed transitions. external pin output driver input driver input protection circuitry bond pa d figure 19a. bus hold circuitry, pins 36-51, 66, 67 external pin output driver input driver input protection circuitry bond pa d v cc p figure 19b. bus hold circuitry, pins 4-6, 68 of processor of processor one processor clock cycle one bus t state one system clk cycle pclk clk phase 1 clock cycle phase 2 clock cycle figure 20. system and processor clock relation- ships 80c286 28 bus states the idle (t i ) state indicates that no data transfers are in progress or requested. the first active state t s is signaled by status line s1 or s0 going low and identifying phase 1 of the processor clock. during t s , the command encoding, the address, and data (for a write operation) are available on the 80c286 output pins. the 82c288 bus controller decodes the status signals and generates multibus compatible read/write command and local transceiver control signals. after t s , the perform command (t c ) state is entered. mem- ory or i/o devices respond to the bus operation during t c , either transferring read data to the cpu or accepting write data. t c states may be repeated as often as necessary to ensure sufficient time for th e memory or i/o device to respond. the ready signal determines whether t c is repeated. a repeated t c state is called a wait state. during hold (t h ), the 80c286 will float all address, data, and status output drivers enabling another bus master to use the local bus. the 80c286 hold input signal is used to place the 80c286 into the t h state. the 80c286 hlda output sig- nal indicates that the cpu has entered t h . pipelined addressing the 80c286 uses a local bus interface with pipelined timing to allow as much time as possible for data access. pipelined timing allows a new bus operation to be initiated every two processor cycles, while allowing each individual bus opera- tion to last for three processor cycles. the timing of the address outputs is pipelined such that the address of the next bus operation becomes available during the current bus operation. or, in other words, the first clock of the next bus operation is overlapped with the last clock of the current bus operation. therefore, address decode and routing logic can operate in advance of the next bus operation. external address latches may hold the address stable for the entire bus operation, and provide additional ac and dc buffer- ing. the 80c286 does not maintain the address of the current bus operation during all t c states. instead, the address for the next bus operation may be emitted during phase 2 of any t c . the address remains valid during phase 1 of the first t c to guarantee hold time, relative to ale, for the address latch inputs. bus control signals the 82c288 bus controller provides control signals; address latch enable (ale), read/write commands, data trans- mit/receive (dt/r ), and data enable (den) that control the address latches, data transceivers, write enable, and output enable for memory and i/o systems. the address latch enable (ale) output determines when the address may be latched. ale provides at least one sys- tem clk period of address hold time from the end of the pre- vious bus operation until the address for the next bus operation appears at the latc h outputs. this address hold time is required to support multibus and common memory systems. the data bus transceivers are controlled by 82c288 outputs data enable (den) and data transmit/receive (dt/r ). den enables the data transceivers; while dt/r controls trans- ceiver direction. den and dt/r are timed to prevent bus contention between the bus master, data bus transceivers, and system data bus transceivers. command timing controls two system timing customizati on options, comm and extension and command delay, are provided on the 80c286 local bus. command extension allows additional time for external devices to respond to a command and is analogous to inserting wait states on the 80c86. external logic can control the duration of any bus operation such that the operation is only as long as necessary. the ready input signal can extend any bus operation for as long as necessary. command delay allows an increase of address or write data setup time to system bus command active for any bus opera- tion by delaying when the system bus command becomes active. command delay is controlled by the 82c288 cmdly input. after t s , the bus controller samples cmdly at each failing edge of clk. if cmdly is high, the 82c288 will not activate the command signal. when cmdly is low, the 82c288 will activate the command signal. after the com- mand becomes active, the cmdly input is not sampled. when a command is delayed, the available response time from command active to return read data or accept write data is less. to customize system bus timing, an address decoder can determine which bus operations require delay- ing the command. the cmdly in put does not affect the tim- ing of ale, den or dt/r . figure 23 illustrates four uses of cmdly. example 1 shows delaying the read command two system clks for cycle n-1 and no delay for cycle n, and example 2 shows delaying the read command one system cl k for cycle n-1 and one sys- tem clk delay for cycle n. hlda ? new cycle new cycle ? hlda ready ? new cycle ready hlda ? new cycle hold t h idle t i command t c status t s hlda hlda new cycle always reset ready ? new cycle figure 21. 80c286 bus states 80c286 29 figure 22. basic bus cycle read bus cycle n clk proc a 23 - a 0 s0 ? s1 ready d 15 - d 0 read bus cycle n + 1 t c t s t c t s t i 1 2 1 2 1 2 1 2 valid read data (n) valid read data (n + 1) valid addr (n) valid addr (n + 1) 2 pclk cycle transfer 2.5 clock cycle address to data valid 2 pclk cycle transfer clk pipelining: valid address (n + 1) available in last phase of bus cycle (n). 80c286 30 bus cycle termination at maximum transfer rates, the 80c286 bus alternates between the status and command states. the bus status sig- nals become inactive after t s so that they may correctly sig- nal the start of the next bus operation after the completion of the current cycle. no ex ternal indication of t c exists on the 80c286 local bus. the bus master and bus controller enter t c directly after t s and continue executing t c cycles until terminated by the assertion of ready . ready operation the current bus master and 82c288 bus controller terminate each bus operation simultaneously to achieve maximum bus operation bandwidth. both are informed in advance by ready active (open-collector output from 82c284) which identifies the last t c cycle of the current bus operation. the bus master and bus controller must see the same sense of the ready signal, thereby requiring ready to be synchro- nous to the system clock. synchronous ready the 82c284 clock generator provides ready synchroniza- tion from both synchronous and asynchronous sources (see figure 24). the synchronous ready input (srdy ) of the clock generator is sampled with the falling edge of clk at the end of phase 1 of each t c . the state of srdy is then broadcast to the bus master and bus controller via the ready output line. asynchronous ready many systems have devices or subsystems that are asyn- chronous to the system clock. as a result, their ready out- puts cannot be guaranteed to meet the 82c284 srdy setup and hold time requirements. but the 82c284 asynchronous ready input (ardy ) is designed to accept such signals. the ardy input is sampled at the beginning of each t c cycle by 82c284 synchronization logic. this provides one system clk cycle time to resolve its value before broadcasting it to the bus master and bus controller. ardy or ardyen must be high at the end of t s . ardy cannot be used to terminate the bus cycle with no wait states. each ready input of the 82c284 has an enable pin (srdyen and ardyen ) to select whether the current bus operation will be terminated by the synchronous or asynchronous ready. either of the ready inputs may terminate a bus opera- tion. these enable inputs are active low and have the same timing as their respective read y inputs. address decode logic usually selects whether the current bus operation should be terminated by ardy or srdy . figure 23. cmdly controls the leading edge of command signal t s t c t c t s t c read cycle n -1 read cycle n valid addr n valid addr (n-1) a 23 - a 0 proc clk clk s1 ? s0 ale ready rd cmdly rd cmdly ex1 ex2 1 2 1 2 1 2 1 2 1 2 80c286 31 data bus control figures 25, 26, and 27 show how the dt/r , den, data bus, and address signals operate for different combinations of read, write, and idle bus operations. dt/r goes active (low) for a read operation. dt/r remains high be fore, during, and between write operations. the data bus is driven with write data during the second phase of t s . the delay in write data timing allows the read data drivers, from a previous read cycle, sufficient time to enter three-state off before the 80c286 cpu begins driv- ing the local data bus for write operations. write data will always remain valid for one sy stem clock past the last t c to provide sufficient hold time fo r multibus or other similar mem- ory or i/o systems. during write-read or write-idle sequences the data bus enters a high impedance state dur- ing the second phase of the processor cycle after the last t c . in a write-write sequence the data bus does not enter a high impedance state between t c and t s . bus usage the 80c286 local bus may be used for several functions: instruction data transfers, data transfers by other bus mas- ters, instruction fetching, processor extension data trans- fers, interrupt acknowledge, and halt/shutdown. this section describes local bus activities which have special signals or requirements. note that i/o transfers take place in exactly the same manner as memory transfers (i.e. to the 80c286 the timing, etc. of an i/o transfer is identical to a memory transfer). hold and hlda hold and hlda allow another bus master to gain control of the local bus by placing the 80c286 bus into the t h state. the sequence of events required to pass control between the 80c286 and another local bus master are shown in figure 28. in this example, the 80c286 is initially in the t h state as signaled by hlda being active. upon leaving t h , as sig- naled by hlda going inactive, a write operation is started. during the write operation another local bus master requests the local bus from the 80c286 as shown by the hold signal. after completing the write operation, the 80c286 performs one t i bus cycle, to guarantee write data hold time, then enters t h as signaled by hlda going active. the cmdly signal and ardy ready are used to start and stop the write bus command, respectively. note that srdy must be inactive or disabled by srdyen to guarantee ardy will terminate the cycle. hold must not be active duri ng the time from the leading edge of reset until 34 clks following the trailing edge of reset unless the 80c286 is in the halt condition. to ensure that the 80c286 remains in t he halt condition until the pro- cessor reset operation is complete, no interrupts should occur after the execution of hlt until 34 clks after the trail- ing edge of the reset pulse. lock the cpu asserts an active lock signal during interrupt- acknowledge cycles, the xchg instruction, and during some descriptor accesses. lock is also asserted when the lock prefix is used. the lo ck prefix may be used with the following asm-286 assembly instructions; movs, ins and outs. for bus cycles other than interrupt-acknowl- edge cycles, lock will be active for the first and subsequent cycles of a series of cycles to be locked. lock will not be shown active during the last cycle to be locked. for the next-to-last cycle, lock will become inactive at the end of the first t c regardless of the number of wait states inserted. for interrupt-acknowledge cycles, lock will be active for each cycle, and will become inactive at the end of the first t c for each cycle regardless of the number of wait- states inserted. instruction fetching the 80c286 bus unit (bu) will fetch instructions ahead of the current instruction being exec uted. this activity is called prefetching. it occurs when the local bus would otherwise be idle and obeys the following rules: a prefetch bus operation starts when at least two bytes of the 6-byte prefetch queue are empty. the prefetcher normally performs word prefetches indepen- dent of the byte alignment of the code segment base in physical memory. the prefetcher will perform only a byte code fetch operation for control transfers to an instruction beginning on a numeri- cally odd physical address. prefetching stops whenever a control transfer or hlt instruc- tion is decoded by the lu and placed into the instruction queue. in real address mode, the prefetcher may fetch up to 6 bytes beyond the last control transfer or hlt instruction in a code segment. in protected mode, the prefetcher will never cause a seg- ment overrun exception. the prefetcher stops at the last physical memory word of the code segment. exception 13 will occur if the program attempts to execute beyond the last full instruction in the code segment. if the last byte of a code segment appears on an even physi- cal memory address, the prefetcher will read the next physi- cal byte of memory (perform a word code fetch). the value of this byte is ignored and any attempt to execute it causes exception 13. 80c286 32 notes: 8. srdyen is active low. 9. if srdyen is high, the state of srdy will not effect ready. 10. ardyen is active low. figure 24. synchronous and asynchronous ready t s t c t s t c t c memory cycle n - 1 memory cycle n 1 2 1 2 1 2 1 2 1 2 valid addr valid addr valid addr (see note 8) (see note 9) (see note 10) a 23 - a 0 clk s0 ? s1 srdy ready ardy proc clk 80c286 33 figure 25. back to back read-write cycle t i t s t c t s t c read cycle write cycle 2 1 2 1 2 1 2 1 2 1 2 t i a 23 - a 0 clk s0 ? s1 mrdc mw tc dt/r d 15 - d 0 den valid read data valid addr valid addr valid write data 80c286 34 processor extension transfers figure 26. back to back write-read cycle figure 27. back to back write-write cycle t i t s t c t s t c write cycle read cycle 2 1 2 1 2 1 2 1 2 1 2 t i clk valid write data a 23 - a 0 s0 ? s1 d 15 - d 0 mrdc mw tc den dt/r valid valid valid read data t i t s t c t s t c write cycle n-1 write cycle n 2 1 2 1 2 1 2 1 2 1 2 t i clk a 23 - a 0 valid addr n-1 valid addr n valid data n-1 valid data n s0 ? s1 d 15 - d 0 mw tc dt/r den (high) 80c286 35 the processor extension interface uses i/o port addresses 00f8(h), and 00fc(h) which are part of the i/o port address range reserved by intersil. an esc instruction with machine status word bits em = 0 and t s = 0 will perform i/o bus operations to one or more of these i/o port addresses inde- pendent of the value of lopl and cpl. esc instructions with memory references enable the cpu to accept pereq inputs for processor extension operand transfers. the cpu will determine the operand starting address and read/write status of the instruction. for each operand transfer, two or three bus operations are performed, one word transfer with i/o port address 00fa(h) and one or two bus operations with memory. three bus operations are required for each word operand aligned on an odd byte address. interrupt acknowledge sequence figure 29 illustrates an interrupt acknowledge sequence per- formed by the 80c286 in response to an intr input. an interrupt acknowledge sequence consists of two inta bus operations. the first allows a master 82c59a programmable interrupt controller (plc) to determine which if any of its slaves should return the interrupt vector. an eight bit vector is read on d 0 -d 7 of the 80c286 during the second inta bus operation to select an interrupt handler routine from the interrupt table. the master cascade enable (mce) signal of the 82c288 is used to enable the cascade address drivers during inta bus operations (see figure 29) onto the local address bus for distribution to slave interrupt controllers via the system address bus. the 80c286 emits the lock signal (active low) during t s of the first inta bus operation. a local bus ?hold? request will not be honor ed until the end of the second inta bus operation. three idle processor clocks are provided by the 80c286 between inta bus operations to allow for the minimum inta to inta time and cas (cascade address) out delay of the 82c59a. the second inta bus operation must always have at least one extra t c state added via logic controlling ready . a 23 -a 0 are in three-state off until after the first t c state of the second inta bus operation. this prevents bus contention between the cascade address drivers and cpu address drivers. the extra t c state allows time for the 80c286 to resume driving the address lines for subsequent bus operations. 80c286 36 notes: 11. status lines are held at a high impedance l ogic one by the 80c286 during a hold state. 12. address, m/io and cod/lnta may start floating during any t c depending on when internal 80c286 bus arbiter decides to release bus to external hold. the float starts in 2 of t c . 13. bhe and lock may start floating after the end of any t c depending on when internal 80c286 bus arbiter decides to release bus to external hold. the float starts in 1 of t c . 14. the minimum hold to hlda ti me is shown. maximum is one t h longer. 15. the earliest hold time is shown. it will always allow a subs equent memory cycle if pending is shown. 16. the minimum hold to hlda time is shown. maximum is a func tion of the instruction, type of bus cycle and other machine state (i.e., interrupts, waits, lock, etc.). 17. asynchronous ready allows term ination of the cycle. synchronous ready does not signal ready in this example. synchronous rea dy state is ignored after ready is si gnaled via the asynchronous input. figure 28. multibus write terminated by asynchronous ready with bus hold valid valid valid (see note 13) (see note 12) (see note 11) (see note 16) (see note 15) not ready not ready not ready not ready (see note 17) ready (see note 17) delay enable v oh t h 2 1 t h 2 1 t h 2 1 bus hold acknowledge t s 2 1 t c 2 1 t c 2 1 t c 2 1 t i 2 1 t h 2 1 bus hold acknowledge write cycle bus cycle type clk hold (see note 14) hlda s1 ? s0 a 23 - a 0 m/io , d 15 - d 0 srdy + ardy + cmdly mw tc dt/r ale cod/inta bhe , lock srdyen ardyen den 80c286 80c284 80c288 t s - status cycle t c - command cycle (see note 11) 80c286 37 local bus usage priorities the 80c286 local bus is shared among several internal units and external hold requests. in case of simultaneous requests, their relati ve priorities are: halt or shutdown cycles the 80c286 externally indicates halt or shutdown conditions as a bus operation. these conditions occur due to a hlt instruction or multiple protection exceptions while attempting to execute one instruction. a halt or shutdown bus operation is signalled when s 1 , s 0 and cod/lnta are low and m/io is high. a 1 high indicates halt, and a 1 low indicates shutdown. the 82c288 bus controller does not issue ale, nor is ready required to terminate a halt or shutdown bus operation. during halt or shutdown, the 80c286 may service pereq or hold requests. a processor extension segment overrun during shutdown will inhibit further service of pereq. either nml or reset will force the 80 c286 out of either halt or shutdown. an intr, if interrupt s are enabled, or a processor extension segment overrun exception will also force the 80c286 out of halt. system configurations the versatile bus structure of the 80c286 mi cro-system, with a full complement of support chips, allows flexible configura- tion of a wide range of systems. the basic configuration, shown in figure 30, is similar to an 80c86 maximum mode system. it includes the cpu plus an 82c59a interrupt con- troller, 82c284 clock generator, and the 82c288 bus con- troller. the 80c86 latches (82c82 and 82c83h) and transceivers (82c86h and 82c87h) may be used in an 80c286 microsystem. as indicated by the dashed lines in figure 30, the ability to add processor extensions is an integral feature of 80c286 based microsystems. the proc essor extension interface allows external hardware to perform special functions and transfer data concurrent with cpu execution of other instruc- tions. full system integrity is maintained because the 80c286 supervises all data transfers and instruction execu- tion for the processor extension. an 80c286 system which includes the 80287 numeric proces- sor extension (npx) uses this interface. the 80c286/80287 system has all the instructions and data types of an 80c86 or 80c88 with 8087 numeric processor extension. the 80287 npx can perform numeric calculations and data transfers concurrently with cpu program execution. numerics code and data have the same integrity as all other information pro- tected by the 80c286 protection mechanism. the 80c286 can overlap chip select decoding and address propagation during the data transfer for the previous bus operation. this information is latched into the 82c82/83h's by ale during the middle of a t s cycle. the latched chip select and address information remains stable during the bus operation while the ne xt cycle's address is being decoded and propagated into the system. decode logic can be implemented with a high speed prom or pal. the optional decode logic shown in figure 30 takes advan- tage of the overlap between addr ess and data of the 80c286 bus cycle to generate advanced memory and i/o select sig- nals. this minimizes system performance degradation caused by address propagation and decode delays. in addi- tion to selecting memory and i/o, the advanced selects may be used with configurations supporting local and system buses to enable the appropriate bus interface for each bus cycle. the cod/lnta and m/io signals are applied to the decode logic to distinguish between interrupt, i/o, code, and data bus cycles. by adding the 82289 bus arbiter chip the 80c286 provides a multibus system bus interface as shown in figure 31. the ale output of the 82c288 for the multibus bus is connected to its cmdly input to delay the start of commands one system clk as required to meet mu ltibus address and write data setup times. this arrangement will add at least one extra t c state to each bus operation which uses the multibus. a second 82c288 bus controller and additional latches and transceivers could be added to the local bus of figure 31. this configuration allows the 80c286 to support an on-board bus for local memory and peripherals, and the multibus for system bus interfacing. (highest) any transfers which assert lock either explic- itly (via the lock instruction prefix) or implic- itly (i.e. some segment descriptor accesses, an interrupt acknowledge sequence, or an xchg with memory). the second of the two byte bus operations required for an odd aligned word operand. the second or third cycle of a processor exten- sion data transfer. local bus request via hold input. processor extension data operand transfer via pereq input. data transfer performed by eu as part of an instruction. (lowest) an instruction pref etch request from bu. the eu will inhibit prefetching two processor clocks in advance of any data transfers to minimize waiting by the eu for a prefetch to finish. 80c286 38 notes: 18. data is ignored. 19. first inta cycle should have at least one wait stat e inserted to meet 82c59a minimum inta pulse width. 20. second inta cycle must have at least one wait state inserted since the cpa will not drive a 23 -a 0 , bhe , and lock until after the first t c state. the cpu imposed one/clock delay prevents has cont ention between cascade address buffer being disabled by mce and address outputs. 21. without the wait state, the 80c286 address will not be valid fo r a memory cycle started immediately after the second inta cy cle. the 82c59a also requires one wait state for minimum inta pulse width. 22. lock is active for the first inta cycle to prevent the 82289 from releasing the bus between inta cycles in a multi-master system. l ock is also active for the second inta cycle. 23. a 23 -a 0 exits three-state off during 2 of the second t c in the inta cycle. figure 29. interrupt acknowledge sequence t c 2 1 inta cycle 1 t s 2 1 t c 2 1 t c 2 1 t i 2 1 t i 2 1 t i 2 1 t s 2 1 t c 2 1 t c 2 1 t s 2 1 inta cycle 2 bus cycle clk s1 ? s0 m/io , lock a 23 - a 0 bhe d 15 - d 0 ready inta mce ale dt/r den (see note 21) (see note 22) (see note 22) don?t care don?t care previous write cycle (see note 18) vector (see note 20) not ready ready (see note 19) not ready ready cod/inta type 80c286 82c288 80c286 39 figure 30. basic 80c286 system configuration v cc reset sync ready enable async ready enable ardyen ardy srdyen shdy reset clk ready s1 s0 f/c efi pclk res x 1 x 2 82c284 clock generator v cc processor extension (optional) mb aen cmdly clk ready s1 s0 m/io dt/r den mce ale inta iowc iorc mw t c mrdc 82c288 bus controller ready error reset clk m/io s1 s0 nmi hold hlda busy peack pereq lock cod/inta d 15 - d 0 a 23 - a 0 bhe intr interrupt acknowledge i/o write i/o read memory write memory read advanced memory and i/o chip selects address bus chip select ir 0 - ir 7 data bus 80c286 cpu decode (optional) stb oe cas 0-2 int inta wr rd d 0 - d 7 oe t 82c82 or 82c83h latch a 0 cs sp/en 82c59a interrupt controller 82c86h or 82c87h trans- ceiver 80c286 40 figure 31. multibus system bus interface sysb/resb reset cbrq always cbqlck s0 s1 ready clk aen m/io lock cbrq busy bprn bpro breq init bclk 82289 bus arbiter x 2 x 1 v cc aen cmdly s0 s1 ready clk mrdc mwtc iorc iowc inta ale mce den dt/r m/io 82c288 bus controller res pclk f/c efi srdy srdyen ardy ardyen reset clk ready s1 s0 82c284 clock generator reset sync ready enable async ready enable processor extension (optional) m/io clk reset ready s1 s0 nmi hold hlda error busy peack pereq 80c286 cpu d 15 - d 0 intr bhe a 23 - a 0 cod/inta lock stb oe 82c83h latch cas 0-2 int inta wr rd sp/en d 0 - d 7 oe t 82c59a interrupt controller 82c87h trans- ceiver a 0 cs chip select address bus ir 0 - ir 7 data bus v cc memory read memory write i/o read i/o write interrupt acknowledge multibus bus arbitration v cc 80c286 41 / absolute maximum ratings thermal information supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0v input, output or i/o voltage applied. . . . . gnd -1.0v to v cc +1.0v storage temperature range . . . . . . . . . . . . . . . . . -65 o c to +150 o c junction temperature, pga . . . . . . . . . . . . . . . . . . . . . . . . . +175 o c plcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150 o c lead temperature (soldering, 10s) . . . . . . . . . . . . . . . . . . . +300 o c (plcc - lead tips only) thermal resistance (typical) ja ( o c/w) jc ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . 35 6 cerdip package . . . . . . . . . . . . . . . . 33 9 maximum package power dissipation pga package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.22w plcc package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2w gate count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22,500 caution: stresses above those listed in ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicat ed in the operational sections of this specification is not impl ied. operating conditions operating voltage range 80c286-10, -12 . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to +5.5v 80c286-16, -20, -25 . . . . . . . . . . . . . . . . . . . . . +4.75v to +5.25v operating temperature range i80c286-10, -12, -16, -20 . . . . . . . . . . . . . . . . . . -40 o c to +85 o c c80c286-12, -16, -20, -25. . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c dc electrical specifications v cc = +5v 10%, t a = 0 o c to +70 o c (c80c286-12), v cc = +5v 5%, t a = 0 o c to +70 o c (c80c286-16, -20, -25), v cc = +5v 10%, t a = -40 o c to +85 o c (i80c286-10, -12), v cc = +5v 5%, t a = -40 o c to +85 o c (i80c286-16, -20) symbol parameter min max units test conditions v il input low voltage -0.5 0.8 v v ih input high voltage 2.0 v cc +0.5 v v ilc clk input low voltage -0.5 1.0 v v ihc clk input high voltage 3.6 v cc +0.5 v v ol output low voltage - 0.4 v i ol = 2.0ma v oh output high voltage 3.0 v cc -0.4 - - vi oh = -2.0ma, i oh = -100 a i i input leakage current -10 10 av in = gnd or v cc pins 29, 31, 57, 59, 61, 63-64 i sh input sustaining current on busy and error pins -30 -500 av in = gnd (see note 28) i bhl input sustaining current low 38 200 av in = 1.0v (see note 24) i bhh input sustaining current high -50 -400 av in = 3.0v (see note 25) i o output leakage current -10 10 av o = gnd or v cc pins 1, 7-8, 10-28, 32-34 i ccop active power supply current - 185 ma 80c286-10 (see note 27) - 220 ma 80c286-12 (see note 27) - 260 ma 80c286-16 (see note 27) - 310 ma 80c286-20 (see note 27) - 410 ma 80c286-25 (see note 27) i ccsb standby power supply current - 5 ma (see note 26) capacitance t a = +25 o c, all measurements referenced to device gnd symbol parameter typ units test conditions c clk clk input capacitance 10 pf freq = 1mhz c in other input capacitance 10 pf c i/o i/o capacitance 10 pf notes: 24. i bhl should be measured after lowering v in to gnd and then raising to 1.0v on the following pins: 36-51, 66, 67. 25. i bhh should be measured after raising v in to v cc and then lowering to 3.0v on the following pins: 4-6, 36-51, 66-68. 26. i ccsb tested with the clock stopped in phase two of the processor clock cycle. v in = v cc or gnd, v cc = v cc (max), outputs unloaded. 27. i ccop measured at 10mhz for the 80c286-10, 12.5mhz for the 80c 286-12, 16mhz for the 80c286-16, 20mhz for the 80c286-20, and 25mhz for the 80c286-25. v in = 2.4v or 0.4v, v cc = v cc (max), outputs unloaded. 28. i sh should be measured after raising v in to v cc and then lowering to gnd on pins 53 and 54. 80c286 42 ac test conditions ac electrical specifications v cc = +5v 10%, t a = 0 o c to +70 o c (c80c286-12), t a = -40 o c to +85 o c (i80c286-10, -12) v cc = +5v 5%, t a = 0 o c to +70 o c (c80c286-16), t a = -40 o c to +85 o c (i80c286-16) ac timings are referenced to 0.8v and 2.0v points of the signals as illustrated in data sheet waveforms, unless otherwise specified symbol parameter 10mhz 12.5mhz 16mhz unit test condition min max min max min max timing requirements 1 system clock (clk) period 50 - 40 - 31 - ns 2 system clock (clk) low time 12 - 11 - 7 - ns at 1.0v 3 system clock (clk) high time 16 - 13 - 11 - ns at 3.6v 17 system clock (clk) rise time - 8 - 8 - 5 ns 1.0v to 3.6v 18 system clock (clk) fall time - 8 - 8 - 5 ns 3.6v to 1.0v 4 asynchronous inputs setup time 20 - 15 - 5 - ns (note 29) 5 asynchronous inputs hold time 20 - 15 - 5 - ns (note 29) 6 reset setup time 19 - 10 - 10 - ns 7 reset hold time 0 - 0 - 0 - ns 8 read data setup time 8 - 5 - 5 - ns 9 read data hold time 4 - 4 - 3 - ns 10 ready setup time 26 - 20 - 12 - ns 11 ready hold time 25 - 20 - 5 - ns 20 input rise/fall times - 10 - 8 - 6 ns 0.8v to 2.0v timing responses 12a status/peack active delay 1 22 1 21 1 18 ns 1, (notes 31, 35) 12b status/peack inactive delay 1 30 1 24 1 20 ns 1, (notes 31, 34) 13 address valid delay 1 35 1 32 1 27 ns 1, (notes 30, 31) 14 write data valid delay 0 40 0 31 0 28 ns 1, (notes 30, 31) 15 address/status/data float delay 0 47 0 32 0 29 ns 2, (note 33) 16 hlda valid delay 0 47 0 25 0 25 ns 1, (notes 31, 36) 19 address valid to status setup time 27 - 22 - 16 - ns 1, (notes 31, 32) notes: 29. asynchronous inputs are intr, nml, hold, pereq, error, and busy. this specification is given only for testing purposes, to a ssure recognition at a specific clk edge. 30. delay from 1.0v on the clk to 0.8v or 2.0v. 31. output load: c l = 100pf. 32. delay measured from address either reaching 0.8v or 2.0v (va lid) to status going active reac hing 0.8v or status going inacti ve reaching 2.0v. 33. delay from 1.0v on the clk to fl oat (no current drive) condition. 34. delay from 1.0v on the clk to 0.8v for min. (hold time) and to 2.0v for max. (inactive delay). 35. delay from 1.0v on the clk to 2.0v for min. (hold time) and to 0.8v for max. (active delay). 36. delay from 1.0v on the clk to 2.0v. test condition i l (constant current source) c l 1 |2.0ma| 100pf 2-6ma (v oh to float) 8ma (v ol to float) 100pf 80c286 43 ac test conditions ac electrical specifications v cc = +5v 5%, t a = 0 o c to +70 o c (c80c286-20, -25), t a = -40 o c to +85 o c (l80c286-20) ac timings are referenced to the 1.5v point of t he signals as illustrated in data sheet waveforms, unless otherwise specified symbol parameter 20mhz 25mhz unit test condition min max min max timing requirements 1 system clock (clk) period 25 - 20 - ns 2 system clock (clk) low time 6 - 5 - ns at 1.0v 3 system clock (clk) high time 9 - 7 - ns at 3.6v 17 system clock (clk) rise time - 4 - 4 ns 1.0v to 3.6v 18 system clock (clk) fall time - 4 - 4 ns 3.6v to 1.0v 4 asynchronous inputs setup time 4 - 4 - ns (note 37) 5 asynchronous inputs hold time 4 - 4 - ns (note 37) 6 reset setup time 10 - 10 - ns 7 reset hold time 0 - 0 - ns 8 read data setup time 3 - 3 - ns 9 read data hold time 2 - 2 - ns 10 ready setup time 10 - 9 - ns 11 ready hold time 3-3-ns 20 input rise/fall times - 6 - 6 ns 0.8v to 2.0v timing responses 12a status/peack active delay 1 15 1 12 ns 1, (notes 39, 42) 12b status/peack inactive delay 1 16 1 13 ns 1, (notes 39, 42) 13 address valid delay 1 23 1 20 ns 1, (notes 38, 39) 14 write data valid delay 0 27 0 24 ns 1, (notes 38, 39) 15 address/status/data float delay 0 25 0 24 ns 2, (note 41) 16 hlda valid delay 0 20 0 19 ns 1, (notes 38, 39) 19 address valid to status setup time 9 - 12 - ns 1, (notes 39, 40) notes: 37. asynchronous inputs are intr, nml, hold, pereq, error, and busy. this specification is given only for testing purposes, to a ssure recognition at a specific clk edge. 38. delay from 1.0v on the clk to 1.5v. 39. output load: c l = 100pf. 40. delay measured from address reachi ng 1.5v to status reaching 1.5v. 41. delay from 1.0v on the clk to fl oat (no current drive) condition. 42. delay from 1.0v on the clk to 1.5v. test condition i l (constant current source) c l 1 |2.0ma| 100pf 2-6ma (v oh to float) 8ma (v ol to float) 100pf 80c286 44 ac specifications (continued) c80c86-12, -16 i80c286-10, -12, -16 ac drive and measure points - clk input note: for ac testing, input rise and fall times are driven at 1ns per volt. figure 32. clk input 4.0v 0.45v 3.6v 3.6v 1.0v 1.0v 1.0v 1.0v 3.6v 3.6v 4.0v 2.0v 0.8v 0.8v 2.0v 0.8v 2.0v t delay (max) t delay (max) t hold t setup clk input 0.45v 2.4v other 0.4v device device input output 80c286 45 c80c286-20, -25 i80c286-20 ac drive and measure points - clk input note: typical output rise/fall time is 6ns. for ac testi ng, input rise and fall times are driven at 1ns per volt. figure 33. ac specifications (continued) clk input 4.0v 0.45v 3.6v 3.6v 1.0v 1.0v 1.0v 1.0v 3.6v 3.6v 4.0v 2.0v 0.8v 0.8v 2.0v 1.5v t delay t hold t setup clk input 0.45v 2.4v other 0.4v device device input output 80c286 46 ac electrical specifications 82c284 and 82c288 timing specifications are given for reference only and no guarantee is implied. 82c284 timing symbol parameter 10mhz 12.5mhz 16mhz unit test condition min max min max min max timing requirements 11 srdy /srdyen setup time 15 - 15 - 10 - ns 12 srdy /srdyen hold time 2-2-1-ns 13 ardy /ardyen setup time 5 - 5 - 3 - ns (note 43) 14 ardy /ardyen hold time 30 - 25 - 20 - ns (note 43) timing responses 19pclk delay 020016015nsc l = 75pf, i ol = 5ma, i oh = 1ma note: 43. these times are given for testing pur poses to ensure a predetermined action. 82c288 timing symbol parameter 10mhz 12.5mhz 16mhz unit test condition min max min max min max timing requirements 12 cmdly setup time 15 - 15 - 10 - ns 13cmdly hold time 1-1-0-ns timing responses 16 ale active delay 1 16 1 16 1 12 ns 17 ale inactive delay - 19 - 19 - 15 ns 19 dt/r read active delay - 23 - 23 - 18 ns c l = 150pf 20 den read active delay - 21 - 21 - 16 ns i ol = 16ma max 21 den read inactive delay 3 23 3 21 5 14 ns i ol = 1ma max 22 dt/r read inactive delay 5 24 5 18 5 14 ns 23 den write active delay - 23 - 23 - 17 ns 24 den write inactive delay 3 23 3 23 3 15 ns 29 command active delay from clk 3 21 3 21 3 15 ns c l = 300pf 30 command inactive delay from clk 3 20 3 20 3 15 ns i ol = 32ma max note: 44. these times are given for testing pur poses to ensure a predetermined action. 80c286 47 waveforms figure 34. major cycle timing note: the modified timing is due to the cmdly signal being active. 3 2 12a 1 12b 19 13 13 13 19 13 9 8 14 11 10 10 11 15 14 13 30 29 24 13 12 12 13 22 23 21 20 19 29 30 13 12 17 19 20 19 12 11 19 16 t i 2 2 2 1 t s 2 1 t c 2 1 t s 2 1 t c 1 t c write cycle bus valid if t s read (t s or t s ) illustrated with one wait state read cycle illustrated with zero wait states cycle type v oh clk v ol s1 ? s0 a 23 - a 0 m/io , cod, bhe , lock ready srdy + srdyen ardy + ardyen plck cmdly mwtc mrdc dt/r den ale inta d 15 - d 0 valid address valid address valid control valid control valid write data valid read data (see note 1) 82c288 82c284 80c286 80c286 48 figure 35. 80c286 asynchronous input signal timing notes: 45. pclk indicates which processor cycle phase will occur on the next clk, pclk may not indicate the correct phase until the first cycle is performed. 46. these inputs are asynchronous. the setup and hold times shown assure recogniti on for testing purposes. figure 36. 80c286 reset input timing and subsequent processor cycle phase note: 47. when reset meets the setup time shown, the next clk will start or repeat 1 of a processor cycle. waveforms (continued) 19 19 5 4 5 4 bus cycle type clk v ch v cl pclk (see note 47) intr, nmi hold, pereq (see note 45) error , busy (see note 46) t x 2 1 clk v ch v cl t x 1 2 1 2 7 6 7 6 reset clk reset v ch v cl t x 1 1 2 (see note 47) (see note 47) 80c286 49 figure 37. exiting and entering hold notes: 48. these signals may not be driven by the 80c286 during the time shown. the worst case in terms of latest float time is shown. 49. the data bus will be driven as shown if the cycle before t i in the diagram was a write t c . 50. the 80c286 puts its status pins in a high impedance logic one state during t h . 51. for hold request set up to hlda, refer to figure 29. 52. bhe and lock are driven at this time but will not become valid until t s . 53. the data bus will remain in a high im pedance state if a read cycle is performed. waveforms (continued) t h 1 bus cycle type v ch clk v cl s1 ? s0 bhe , lock 80c286 2 hlda clk d 15 - d 0 pclk 80c284 a 23 - a 0 , m/io, cod/inta 1 2 1 2 1 2 16 16 15 15 15 15 14 13 12a 12b t s or t i t i t h (see note 51) (see note 50) (see note 48) (see note 49) (see note 53) (see note 52) (see note 50) if t s if npx transfer valid valid if write 80c286 50 assuming word-aligned memory operand. if odd aligned, 80c286 transfers to/from me mory byte-at-a-time with two memory cycles. figure 38. 80c286 pereq/peack timing for one transfer only notes: 54. peack always goes active during the first bus operation of a processor extension dat a operand transfer sequence. the first bus opera - tion will be either a memory read at operand address or i/o read at port address 00fa(h). 55. to prevent a second processor ext ension data operand transfer, the worst case maximum time (shown above) is 3 x - 12a max - min . the actual configuration dependent , maximum time is: 3 x - 12a max - min + n x 2 x . n is the number of extra t c states added to either the first or second bus operation of the processo r extension data op erand transfer sequence. figure 39. initial 80c286 pin state during reset notes: 56. setup time for reset may be violated with the consideration that 1 of the processor clock may begin one system clk period later. 57. setup and hold times for reset must be met for proper operation, but reset may occur during 1 or 2. 58. the data bus is only guaranteed to be in a high impedance state at the time shown. waveforms (continued) 1 12a 12b 4 5 t i 2 bus cycle type v ch clk v cl 1 s1 ? s0 a23 - a0 m/io, peack pereq 2 2 1 2 1 2 1 t s t c t s t c t i i/o read if proc. ext. to memory memory read if memory to proc. ext. memory write if proc. ext. to memory i/o write if memory to proc. ext. memory address if proc. ext. to memory transfer i/o port address 00fa(h) if memory to proc. ext. transfer i/o port address 00fa(h) if proc. ext. to memory transfer memory address if memory to proc. ext. transfer (see note 54) (see note 55) cod inta 1 4 1 4 1 6 7 12b 13 13 13 15 16 19 2 bus cycle type v ch clk v cl 1 reset a 23 - a 0 (see note 56) 2 1 2 1 2 1 2 unknown unknown unknown unknown unknown s1 ? s0 bhe m/io cod/inta lock data hlda peack t x t x t x t i at least (see note 57) (see note 58) 16 clk periods 80c286 51 80c286 instruction set summary instruction timing notes the instruction clock counts listed below establish the maxi- mum execution rate of the 80c286. with no delays in bus cycles, the actual clock count of an 80c286 program will average 5% more than the calculated clock count, due to instruction sequences which ex ecute faster than they can be fetched from memory. to calculate elapsed times for instruction sequences, multi- ply the sum of all instruction cl ock counts, as listed in the table below, by the processor clock period. an 12.5mhz pro- cessor clock has a clock period of 80 nanoseconds and requires an 80c286 system clock (clk input) of 25mhz. instruction clock count assumptions 1. the instruction has been perfected, decoded and is ready for execution. control transfer instruction clock counts include all time required to fetch, decode, and prepare the next instruction for execution. 2. bus cycles do not r equire wait states. 3. there are no processor extension data transfer or local bus hold requests. 4. no exceptions occur duri ng instruction execution. instruction set summary notes addressing displacements select ed by the mod field are not shown. if necessary they appear after the instruction fields shown. above/below refers to unsigned value. greater refers to more positive signed values. less refers to less positive (more negative) signed values if d = 1, then ?to? register ; if d = 0 then ?from? register if w = 1, then word instruction; if w = 0, then byte instruction if s = 0, then 16-bit immediate data form the operand if s = 1, then an immediate data byte is sign-extended to form the 16-bit operand x don?t care z used for string primitives for comparison with zf flag if two clock counts are given, the smaller refers to a register operand and the larger refers to a memory operand * = add one clock if offset calculation requires summing 3 elements n = number of times repeated m = number of bytes of co de in next instruction level (l) - lexical nesting level of the procedure the following comments descr ibe possible exceptions, side effects and allowed usage for instructions in both operating modes of the 80c286. figure 40a. short opcode format example figure 40b. long opcode format example figure 40. 80c286 instruction format examples waveforms (continued) low disp/data high disp/data low data high data opcode mod reg r/m dw byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 7654321076543210 register operand registers to use in offset calculation register operand/extension of opcode register mode/memory mode with displacement length word/byte operation direction is to register direction is from register operation (ins truction) code low disp high disp byte 5 byte 4 byte 3 byte 2 byte 1 long opcode mod reg r/m 765432107654321076543210 80c286 52 real address mode only 1. this is a protected mode in struction. attempted execu- tion in real address mode will result in an undefined opcode exception (6). 2. a segment overrun exception (13) will occur if a word operand references at offset ffff(h) is attempted. 3. this instruction may be exec uted in real address mode to initialize the cpu for protected mode. 4. the iopl and nt fields will remain 0. 5. processor extension segment overrun interrupt (9) will occur if the operand ex ceeds the segment limit. either mode 6. an exception may occur, depending on the value of the operand. 7. lock is automatically asserted regardless of the pres- ence or absence of the lock instruction prefix. 8. lock does not remain active between all operand transfers. protected virtual address mode only 9. a general protection exception (13) will occur if the mem- ory operand cannot be used due to either a segment limit or access rights violation. if a stack segment limit is vio- lated, a stack segment overrun exception (12) occurs. 10. for segment load operations, the cpl, rpl and dpl must agree with privilege rules to avoid an exception. the segment must be present to avoid a not-present exception (11). if the ss regist er is the destination and a segment not-present violation occurs, a stack exception (12) occurs. 11. all segment descriptor accesses in the gdt or ldt made by this instruction will automatically assert lock to main- tain descriptor integrity in multiprocessor systems. 12. jmp, call, int, ret, iret instructions referring to another code segment will cause a general protection exception (13) if any privilege rule is violated. 13. a general protection exception (13) occurs if cpl 0. 14. a general protection exception (13) occurs if cpl > iopl. 15. the if field of the flag word is not updated if cpl > iopl. the iopl field is updated only if cpl = 0. 16. any violation of privilege rules as applied to the selector operand does not cause a pr otection exception; rather, the instruction does not return a result and the zero flag is cleared. 17. if the starting address of the memory operand violates a segment limit, or an invalid access is attempted, a gen- eral protection exception (13) will occur before the esc instruction is executed. a stack segment overrun excep- tion (12) will occur if the stack limit is violated by the operand?s starting address. if a segment limit is violated during an attempted data transfer then a processor extension segment overrun exception (9) occurs. 18. the destination of an in t, jmp, call, ret or iret instruction must be in the de fined limit of a code segment or a general protection exception (13) will occur. 80c286 instruction set summary function format clock count comments real addres s mode pro- tected virtual address mode real addres s mode pro- tected virtual address mode data transfer mov = move register to register/mem- ory 1000100w mod reg r/m 2, 3 (note 59) 2, 3 (note 59) 29 register/memory to regis- ter 1000101w mod reg r/m 2, 5 (note 59) 2, 5 (note 59) 29 immediate to register/mem- ory 1100011w mod 000 r/m data data if w = 1 2, 3 (note 59) 2, 3 (note 59) 29 immediate to register 1011w reg data data if w = 1 22 memory to accumulator 1010000w addr-low addr-high 5 5 2 9 80c286 53 accumulator to memory 1010001w addr-low addr-high 3 3 2 9 register/memory to seg- ment register 10001110 mod 0 reg r/m 2, 5 (note 59) 17, 19 (note 59) 2 9, 10, 11 segment register to regis- ter/memory 10001100 mod 0 reg r/m 2, 3 (note 59) 2, 3 (note 59) 29 push = push memory 11111111 mod 110 r/m 5 (note 59) 5 (note 59) 29 register 01010 reg 3 3 2 9 segment register 000 reg 110 33 29 immediate 011010s0 data data if s = 0 33 29 pusha = push all 01100000 17 17 2 9 pop = pop memory 10001111 mod 000 r/m 5 (note 59) 5 (note 59) 29 register 01011 reg 5 5 2 9 segment register 000 reg 111 (reg 01) 5 20 2 9, 10, 11 popa = pop all 01100001 19 19 2 9 xchg = exchange register/memory with reg- ister 1000011w mod reg r/m 3, 5 (note 59) 3, 5 (note 59) 2, 7 7, 9 register with accumulator 10010 reg 3 3 in = input from fixed port 1110010w port 5 5 14 variable port 1110110w 5 5 14 out = output to fixed port 1110011w port 3 3 14 variable port 1110111w 3 3 14 xlat = translate byte to al 11010111 5 5 9 80c286 instruction set summary (continued) function format clock count comments real addres s mode pro- tected virtual address mode real addres s mode pro- tected virtual address mode 80c286 54 lea = load ea to register 10001101 mod reg r/m 3 (note 59) 3 (note 59) lds = load pointer to ds 11000101 mod reg r/m (mod 11) 7 (note 59) 21 (note 59) 2 9, 10, 11 les = load pointer to es 11000100 mod reg r/m (mod 1) 7 (note 59) 21 (note 59) 2 9, 10, 11 lahf load ah with flags 10011111 2 2 sahf = store ah into flags 10011110 2 2 pushf = push flags 10011100 3 3 2 9 popf = pop flags 10011101 5 5 2, 4 9, 15 arlthmetlc add = add reg/memory with register to either 000000dw mod reg r/m 2, 7 (note 59) 2, 7 (note 59) 29 immediate to regis- ter/memory 100000sw mod 000 r/m data data if sw = 01 3, 7 (note 59) 3, 7 (note 59) 29 immediate to accumulator 0000010w data data if w = 1 33 adc = add with carry reg/memory with register to either 000100dw mod reg r/m 2, 7 (note 59) 2, 7 (note 59) 29 immediate to regis- ter/memory 100000sw mod 010 r/m data data if sw = 01 3, 7 (note 59) 3, 7 (note 59) 29 immediate to accumulator 0001010w data data if w = 1 33 inc = increment register/memory 1111111w mod 000 r/m 2, 7 (note 59) 2, 7 (note 59) 29 register 01000 reg 2 2 sub = subtract reg/memory and register to either 001010dw mod reg r/m 2, 7 (note 59) 2, 7 (note 59) 29 80c286 instruction set summary (continued) function format clock count comments real addres s mode pro- tected virtual address mode real addres s mode pro- tected virtual address mode 80c286 55 immediate from regis- ter/memory 100000sw mod 101 r/m data data if sw = 01 3, 7 (note 59) 3, 7 (note 59) 29 immediate from accumula- tor 0010110w data data if w = 1 33 sbb = subtract with borrow reg/memory and register to either 000110dw mod reg r/m 2, 7 (note 59) 2, 7 (note 59) 29 immediate from regis- ter/memory 100000sw mod 011 r/m data data if sw = 01 3, 7 (note 59) 3, 7 (note 59) 29 immediate from accumula- tor 0001110w data data if w = 1 33 dec = decrement register/memory 1111111w mod 001 r/m 2, 7 (note 59) 2, 7 (note 59) 29 register 01001 reg 2 2 cmp = compare register/memory with reg- ister 0011101w mod reg r/m 2, 6 (note 59) 2, 6 (note 59) 29 register with regis- ter/memory 0011100w mod reg r/m 2, 7 (note 59) 2, 7 (note 59) 29 immediate with regis- ter/memory 100000sw mod 111 r/m data data if sw = 01 3, 6 (note 59) 3, 6 (note 59) 29 immediate with accumula- tor 0011110w data data if w = 1 33 neg = change sign 1111011w mod 011 r/m 27 (note 59) 27 aaa = ascii adjust for add 00110111 3 3 daa = decimal adjust for add 00100111 3 3 aas = ascii adjust for subtract 00111111 3 3 das = decimal adlust for subtract 00101111 3 3 mul = multiply (unsigned) 1111011w mod 100 r/m 80c286 instruction set summary (continued) function format clock count comments real addres s mode pro- tected virtual address mode real addres s mode pro- tected virtual address mode 80c286 56 register - byte 13 13 register - word 21 21 memory - byte 16 (note 59) 16 (note 59) 29 memory - word 24 (note 59) 24 (note 59) 29 imul = integer multiply (signed) 1111011w mod 101 r/m register - byte 13 13 register - word 21 21 memory - byte 16 (note 59) 16 (note 59) 29 memory - word 24 (note 59) 24 (note 59) 29 imul = interger immediate multiply (signed) 011010s1 mod reg r/m data data if s = 0 21, 24 (note 59) 21, 24 (note 59) 29 div = divide (unsigned) 1111011w mod 110 r/m register - byte 14 14 6 6 register - word 22 22 6 6 memory - byte 17 (note 59) 17 (note 59) 2, 6 6, 9 memory - word 25 (note 59) 25 (note 59) 2, 6 6, 9 idiv = integer divide (signed) 1111011w mod 111 r/m register - byte 17 17 6 6 register - word 25 25 6 6 memory - byte 20 (note 59) 20 (note 59) 2, 6 6, 9 memory - word 28 (note 59) 28 (note 59) 2, 6 6, 9 aam = ascii adjust for multiply 11010100 00001010 16 16 80c286 instruction set summary (continued) function format clock count comments real addres s mode pro- tected virtual address mode real addres s mode pro- tected virtual address mode 80c286 57 aad = ascii adjust for divide 11010101 00001010 14 14 cbw = convert byte to word 10011000 2 2 cwd = convert word to double word 10011001 2 2 logic shift/rotate instructions register/memory by 1 1101000w mod ttt r/m 2, 7 (note 59) 2, 7 (note 59) 29 register/memory by cl 1101001w mod ttt r/m 5+n, 8+n (note 59) 5+n, 8+n (note 59) 29 register/memory by count 1100000 mod ttt r/m count 5+n, 8+n (note 59) 5+n, 8+n (note 59) 29 ttt instruction 000 rol 001 ror 010 rcl 011 rcr 100 shl/sal 101 shr 111 sar and = and reg/memory and register to either 001000dw mod reg r/m 2, 7 (note 59) 2, 7 (note 59) 29 immediate to regis- ter/memory 1000000w mod 100 r/m data data if w = 1 3, 7 (note 59) 3, 7 (note 59) 29 immediate to accumulator 0010010w data data if w = 1 33 test = and function to flags, no result register/memory and reg- ister 1000010w mod reg r/m 2, 6 (note 59) 2, 6 (note 59) 29 80c286 instruction set summary (continued) function format clock count comments real addres s mode pro- tected virtual address mode real addres s mode pro- tected virtual address mode 80c286 58 immediate data and regis- ter/memory 1111011w mod 000 r/m data data if w = 1 3, 6 (note 59) 3, 6 (note 59) 29 immediate data and accu- mulator 1010100w data data if w = 1 33 or = or reg/memory and register to either 000010dw mod reg r/m 2, 7 (note 59) 2, 7 (note 59) 29 immediate to regis- ter/memory 1000000w mod 001 r/m data data if w = 1 3, 7 (note 59) 3, 7 (note 59) 29 immediate to accumulator 0000110w data data if w = 1 33 xor = exclusive or reg/memory and register to either 001100dw mod reg r/m 2, 7 (note 59) 2, 7 (note 59) 29 immediate to regis- ter/memory 1000000w mod reg r/m data data if w = 1 3, 7 (note 59) 3, 7 (note 59) 29 immediate to accumulator 0011010w data data if w = 1 33 not = invert regis- ter/memory 1111011w mod 010 r/m 2, 7 (note 59) 2, 7 (note 59) 29 string manipulation movs = move byte/word 1010010w 5 5 2 9 cmps = compare byte/word 1010011w 8 8 2 9 scas = scan byte/word 1010111w 7 7 2 9 lods = load byte/word to al/ax 1010110w 5 5 2 9 stos = store byte/word from al/a 1010101w 3 3 2 9 ins = input byte/word from dx port 0110110w 5 5 2 9, 14 outs = output byte/word to dx port 0110111w 5 5 2 9, 14 80c286 instruction set summary (continued) function format clock count comments real addres s mode pro- tected virtual address mode real addres s mode pro- tected virtual address mode 80c286 59 all intersil u.s. products are manufactured, asse mbled and tested utilizin g iso9000 quality systems. intersil corporation?s quality certifications c an be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com 80c286 repeated by count in cx movs = move string 11110011 1010010w 5 + 4n 5 + 4n 2 9 cmps = compare string 1111001z 1010011w 5 + 9n 5 + 9n 2, 8 8, 9 scas = scan string 1111001z 1010111w 5 + 8n 5 + 8n 2, 8 8, 9 lods = load string 11110011 1010110w 5 + 4n 5 + 4n 2, 8 8, 9 stos = store string 11110011 1010101w 4 + 3n 4 + 3n 2, 8 8, 9 ins = input string 11110011 0110110w 5 + 4n 5 + 4n 2 9, 14 outs = output string 11110011 0110111w 5 + 4n 5 + 4n 2 9, 14 control transfer call = call direct within segment 11101000 disp-low disp-high 7 + m 7 + m 2 18 register/memory indirect within segment 11111111 mod 010 r/m 7 + m, 11 + m (note 59) 7 + m, 11 + m (note 59) 2, 8 8, 9, 18 direct intersegment 10011010 segment offset 13 + m 26 + m 2 11, 12,18 protected mode only (direct intersegment) segment selector via call gate to same privilege level 41 + m 8, 11, 12, 18 via call gate to different privilege level, no parameters 82 + m 8, 11, 12, 18 80c286 instruction set summary (continued) function format clock count comments real addres s mode pro- tected virtual address mode real addres s mode pro- tected virtual address mode 60 via call gate to different privilege level, x param- eters 86 + 4x + m 8, 11, 12, 18 via tss 177 + m 8, 11, 12, 18 via task gate 182 + m 8, 11, 12, 18 indirect intersegment 11111111 mod 011 r/m mod 11 16 + m (note 59) 29 + m (note 59) 2 8, 9, 11, 12, 18 protected mode only (i ndirect intersegment) via call gate to same privilege level 44 + m (note 59) 8, 9, 11, 12, 18 via call gate to different privilege level, no parameters 83 + m (note 59) 8, 9, 11, 12, 18 via call gate to different privilege level, x param- eters 90 + 4x + m (note 59) 8, 9, 11, 12, 18 via tss 180 + m (note 59) 8, 9, 11, 12, 18 protected mode only (indirec t intersegment) (continued) via task gate 185 + m (note 59) 8, 9, 11, 12, 18 jmp = unconditional jump short/long 11101011 disp-low 7 + m 7 + m 18 direct within segment 11101001 disp-low disp-high 7 + m 7 + m 18 register/memory indirect within segment 11111111 mod 100 r/m 7 + m, 11 + m (note 59) 7 + m, 11 + m (note 59) 29, 18 direct intersegment 11101010 segment offset 11 + m 23 + m 11, 12, 18 protected mode only (direct intersegment) segment selector via call gate to same privilege level 38 + m 8, 11,12,18 via tss 175 + m 8, 11,12,18 via task gate 180 + m 8, 11,12,18 indirect intersegment 11111111 mod 101 r/m mod 11 15 + m (note 59) 26 + m (note 59) 2 8, 9, 11, 12, 18 protected mode only (i ndirect intersegment) 80c286 instruction set summary (continued) function format clock count comments real addres s mode pro- tected virtual address mode real addres s mode pro- tected virtual address mode 80c286 |
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